From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Michael Roth" <michael.roth@amd.com>
Subject: Re: [PATCH 4/4] i386/cpu: Update how the EBX register of CPUID 0x8000001F is set
Date: Thu, 13 Oct 2022 15:01:53 +0100 [thread overview]
Message-ID: <Y0gaUYeH3Wzojd6W@work-vm> (raw)
In-Reply-To: <5822fd7d02b575121380e1f493a8f6d9eba2b11a.1664550870.git.thomas.lendacky@amd.com>
* Tom Lendacky (thomas.lendacky@amd.com) wrote:
> Update the setting of CPUID 0x8000001F EBX to clearly document the ranges
> associated with fields being set.
>
> Fixes: 6cb8f2a663 ("cpu/i386: populate CPUID 0x8000_001F when SEV is active")
> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
> ---
> target/i386/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 1db1278a59..d4b806cfec 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -5853,8 +5853,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> if (sev_enabled()) {
> *eax = 0x2;
> *eax |= sev_es_enabled() ? 0x8 : 0;
> - *ebx = sev_get_cbit_position();
> - *ebx |= sev_get_reduced_phys_bits() << 6;
> + *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
> + *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
> }
> break;
> default:
> --
> 2.37.3
>
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
next prev parent reply other threads:[~2022-10-13 14:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 15:14 [PATCH 0/4] Qemu SEV reduced-phys-bits fixes Tom Lendacky
2022-09-30 15:14 ` [PATCH 1/4] qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1 Tom Lendacky
2022-10-13 13:22 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 2/4] qemu-options.hx: Update the reduced-phys-bits documentation Tom Lendacky
2022-10-13 13:29 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 3/4] i386/sev: Update checks and information related to reduced-phys-bits Tom Lendacky
2022-10-13 13:31 ` Dr. David Alan Gilbert
2022-09-30 15:14 ` [PATCH 4/4] i386/cpu: Update how the EBX register of CPUID 0x8000001F is set Tom Lendacky
2022-10-13 14:01 ` Dr. David Alan Gilbert [this message]
2023-01-04 18:13 ` [PATCH 0/4] Qemu SEV reduced-phys-bits fixes Tom Lendacky
2023-01-09 15:05 ` Daniel P. Berrangé
2023-04-21 8:48 ` Paolo Bonzini
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