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* [PULL 00/10] riscv-to-apply queue
@ 2022-10-14  7:58 Alistair Francis
  2022-10-14  7:58 ` [PULL 01/10] hw/riscv: Update comment for qtest check in riscv_find_firmware() Alistair Francis
                   ` (10 more replies)
  0 siblings, 11 replies; 13+ messages in thread
From: Alistair Francis @ 2022-10-14  7:58 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 2ba341b3694cf3cff7b8a1df4cc765900d5c4f60:

  Merge tag 'kraxel-20221013-pull-request' of https://gitlab.com/kraxel/qemu into staging (2022-10-13 13:55:53 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221014

for you to fetch changes up to 47566421f029b0a489b63f8195b3ff944e017056:

  target/riscv: pmp: Fixup TLB size calculation (2022-10-14 14:36:19 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.2

* Update qtest comment
* Fix coverity issue with Ibex SPI
* Move load_image_to_fw_cfg() to common location
* Enable booting S-mode firmware from pflash on virt machine
* Add disas support for vector instructions
* Priority level fixes for PLIC
* Fixup TLB size calculation when using PMP

----------------------------------------------------------------
Alistair Francis (1):
      target/riscv: pmp: Fixup TLB size calculation

Bin Meng (1):
      hw/riscv: Update comment for qtest check in riscv_find_firmware()

Jim Shu (2):
      hw/intc: sifive_plic: fix hard-coded max priority level
      hw/intc: sifive_plic: change interrupt priority register to WARL field

Sunil V L (3):
      hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
      hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
      hw/riscv: virt: Enable booting S-mode firmware from pflash

Wilfred Mallawa (2):
      hw/ssi: ibex_spi: fixup coverity issue
      hw/ssi: ibex_spi: fixup/add rw1c functionality

Yang Liu (1):
      disas/riscv.c: rvv: Add disas support for vector instructions

 include/hw/nvram/fw_cfg.h      |   21 +
 include/hw/riscv/boot.h        |    1 +
 include/hw/ssi/ibex_spi_host.h |    4 +-
 disas/riscv.c                  | 1432 +++++++++++++++++++++++++++++++++++++++-
 hw/arm/boot.c                  |   49 --
 hw/intc/sifive_plic.c          |   25 +-
 hw/loongarch/virt.c            |   33 -
 hw/nvram/fw_cfg.c              |   32 +
 hw/riscv/boot.c                |   33 +-
 hw/riscv/virt.c                |   32 +-
 hw/ssi/ibex_spi_host.c         |  166 +++--
 target/riscv/pmp.c             |   12 +
 12 files changed, 1675 insertions(+), 165 deletions(-)


^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PULL 00/10] riscv-to-apply queue
@ 2025-03-19  8:02 Alistair Francis
  0 siblings, 0 replies; 13+ messages in thread
From: Alistair Francis @ 2025-03-19  8:02 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:

  Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250319

for you to fetch changes up to ffe4db11f8aed79c7ec7d3ebd92674a1cfab4fe7:

  target/riscv: Add check for 16-bit aligned PC for different priv versions. (2025-03-19 17:11:46 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 10.0

* Fix broken emulation link
* Optimize the memory probing for vector fault-only-first loads
* Fix access permission checks for CSR_SSP
* Fixes a bug against `ssamoswap` behavior in M-mode
* Fix IOMMU process directory table walk
* Fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()
* Enhance VSTART and VL checks for vector instructions
* Fix handling of cpu mask in riscv_hwprobe syscall
* Add check for 16-bit aligned PC for different priv versions

----------------------------------------------------------------
Chao Liu (2):
      target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
      target/riscv: fix handling of nop for vstart >= vl in some vector instruction

Daniel Henrique Barboza (1):
      target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()

Deepak Gupta (2):
      target/riscv: fix access permission checks for CSR_SSP
      target/riscv: fixes a bug against `ssamoswap` behavior in M-mode

Jason Chien (1):
      hw/riscv/riscv-iommu: Fix process directory table walk

Paolo Savini (1):
      optimize the memory probing for vector fault-only-first loads.

Richard Henderson (1):
      linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall

Santiago Monserrat Campanello (1):
      docs/about/emulation: Fix broken link

Yu-Ming Chang (1):
      target/riscv: Add check for 16-bit aligned PC for different priv versions.

 docs/about/emulation.rst                      |   2 +-
 hw/riscv/riscv-iommu-bits.h                   |   6 +-
 target/riscv/cpu.h                            |  12 ++
 target/riscv/vector_internals.h               |  12 +-
 hw/riscv/riscv-iommu.c                        |   4 +-
 linux-user/syscall.c                          |  55 ++++----
 target/riscv/csr.c                            |   7 +-
 target/riscv/op_helper.c                      |   8 +-
 target/riscv/translate.c                      |   4 +-
 target/riscv/vcrypto_helper.c                 |  32 ++---
 target/riscv/vector_helper.c                  | 186 ++++++++++++++------------
 target/riscv/vector_internals.c               |   4 +-
 target/riscv/insn_trans/trans_rvi.c.inc       |   8 +-
 target/riscv/insn_trans/trans_rvzicfiss.c.inc |  17 +++
 14 files changed, 214 insertions(+), 143 deletions(-)


^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-03-19  8:04 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-10-14  7:58 [PULL 00/10] riscv-to-apply queue Alistair Francis
2022-10-14  7:58 ` [PULL 01/10] hw/riscv: Update comment for qtest check in riscv_find_firmware() Alistair Francis
2022-10-14  7:58 ` [PULL 02/10] hw/ssi: ibex_spi: fixup coverity issue Alistair Francis
2022-10-14  7:58 ` [PULL 03/10] hw/ssi: ibex_spi: fixup/add rw1c functionality Alistair Francis
2022-10-14  7:58 ` [PULL 04/10] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location Alistair Francis
2022-10-14  7:58 ` [PULL 05/10] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel Alistair Francis
2022-10-14  7:58 ` [PULL 06/10] hw/riscv: virt: Enable booting S-mode firmware from pflash Alistair Francis
2022-10-14  7:58 ` [PULL 07/10] disas/riscv.c: rvv: Add disas support for vector instructions Alistair Francis
2022-10-14  7:58 ` [PULL 08/10] hw/intc: sifive_plic: fix hard-coded max priority level Alistair Francis
2022-10-14  7:58 ` [PULL 09/10] hw/intc: sifive_plic: change interrupt priority register to WARL field Alistair Francis
2022-10-14  7:58 ` [PULL 10/10] target/riscv: pmp: Fixup TLB size calculation Alistair Francis
2022-10-16 21:52 ` [PULL 00/10] riscv-to-apply queue Stefan Hajnoczi
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2025-03-19  8:02 Alistair Francis

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