[PATCH] target/hppa: Fix fid instruction emulation

[PATCH] target/hppa: Fix fid instruction emulation

[Helge Deller]

The fid instruction (Floating-Point Identify) puts the FPU model and
revision into the Status Register. Since those values shouldn't be 0,
store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit)
would return.

Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index c7a7e997f9..3ba5f9885a 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -388,10 +388,8 @@ fmpyfadd_d      101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5    ra3=%rc32

 # Floating point class 0

-# FID.  With r = t = 0, which via fcpy puts 0 into fr0.
-# This is machine/revision = 0, which is reserved for simulator.
-fcpy_f          001100 00000 00000 00000 000000 00000   \
-                &fclass01 r=0 t=0
+# FID.  Basically like fcpy with r = t = 0. Puts machine/revision into fr0.
+fid_f           001100 00000 00000 000 00 000000 00000

 fcpy_f          001100 ..... ..... 010 00 ...... .....  @f0c_0
 fabs_f          001100 ..... ..... 011 00 ...... .....  @f0c_0
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index d15b9e27c7..845c00fc4a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3622,6 +3622,17 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
     tcg_gen_mov_i32(dst, src);
 }

+static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
+{
+    nullify_over(ctx);
+#if TARGET_REGISTER_BITS == 64
+    save_frd(0, tcg_const_i64(0x13080000000000)); /* PA8700 (PCX-W2) */
+#else
+    save_frd(0, tcg_const_i64(0x0f080000000000)); /* PA7300LC (PCX-L2) */
+#endif
+    return nullify_end(ctx);
+}
+
 static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a)
 {
     return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f);

Re: [PATCH] target/hppa: Fix fid instruction emulation

[Richard Henderson]

On 10/27/22 16:31, Helge Deller wrote:
> The fid instruction (Floating-Point Identify) puts the FPU model and
> revision into the Status Register. Since those values shouldn't be 0,
> store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit)
> would return.
> 
> Signed-off-by: Helge Deller <deller@gmx.de>
> 
> diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
> index c7a7e997f9..3ba5f9885a 100644
> --- a/target/hppa/insns.decode
> +++ b/target/hppa/insns.decode
> @@ -388,10 +388,8 @@ fmpyfadd_d      101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5    ra3=%rc32
> 
>   # Floating point class 0
> 
> -# FID.  With r = t = 0, which via fcpy puts 0 into fr0.
> -# This is machine/revision = 0, which is reserved for simulator.

Is there something in particular for which this is failing?
Per the manual, 0 means simulator, which we are.
So far we haven't identified as a particular cpu, have we?


> +static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
> +{
> +    nullify_over(ctx);
> +#if TARGET_REGISTER_BITS == 64
> +    save_frd(0, tcg_const_i64(0x13080000000000)); /* PA8700 (PCX-W2) */
> +#else
> +    save_frd(0, tcg_const_i64(0x0f080000000000)); /* PA7300LC (PCX-L2) */
> +#endif
> +    return nullify_end(ctx);
> +}

Missing ULL suffix.


r~

Re: [PATCH] target/hppa: Fix fid instruction emulation

[Helge Deller]

On 10/27/22 11:48, Richard Henderson wrote:
> On 10/27/22 16:31, Helge Deller wrote:
>> The fid instruction (Floating-Point Identify) puts the FPU model and
>> revision into the Status Register. Since those values shouldn't be 0,
>> store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit)
>> would return.
>>
>> Signed-off-by: Helge Deller <deller@gmx.de>
>>
>> diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
>> index c7a7e997f9..3ba5f9885a 100644
>> --- a/target/hppa/insns.decode
>> +++ b/target/hppa/insns.decode
>> @@ -388,10 +388,8 @@ fmpyfadd_d      101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5    ra3=%rc32
>>
>>   # Floating point class 0
>>
>> -# FID.  With r = t = 0, which via fcpy puts 0 into fr0.
>> -# This is machine/revision = 0, which is reserved for simulator.
>
> Is there something in particular for which this is failing?
> Per the manual, 0 means simulator, which we are.

I can't say yet if it's really failing.
I noticed it while trying to get MPE/iX installed in a hppa guest.
In some doc (sorry don't know which one right now) I saw that 0/0
values were illegal values, which is why I changed the values to
become those of a PA7300LC CPU from a  B160L machine (which
we currently emulate with the hppa SeaBIOS).

> So far we haven't identified as a particular cpu, have we?

Not really, but as just mentioned the SeaBIOS reports back a B160L.
If we support more machines this needs to be adjusted.

>> +static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
>> +{
>> +    nullify_over(ctx);
>> +#if TARGET_REGISTER_BITS == 64
>> +    save_frd(0, tcg_const_i64(0x13080000000000)); /* PA8700 (PCX-W2) */
>> +#else
>> +    save_frd(0, tcg_const_i64(0x0f080000000000)); /* PA7300LC (PCX-L2) */
>> +#endif
>> +    return nullify_end(ctx);
>> +}
>
> Missing ULL suffix.

Will fix.

Helge