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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org, f4bug@amsat.org
Subject: Re: [PATCH  v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access
Date: Fri, 11 Nov 2022 20:41:15 +0100	[thread overview]
Message-ID: <Y26lWx2rlMn8sYYV@toto> (raw)
In-Reply-To: <20221111182535.64844-11-alex.bennee@linaro.org>

On Fri, Nov 11, 2022 at 06:25:25PM +0000, Alex Bennée wrote:
> Both of these functions deal with CPU based access (as is evidenced by
> the secure check straight after). Use the new MEMTXATTRS_CPU
> constructor to ensure the correct CPU id is filled in should it ever
> be needed by any devices later.

Looks good to me!

Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>

> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>  target/microblaze/helper.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index 98bdb82de8..655be3b320 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -44,7 +44,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>      MicroBlazeMMULookup lu;
>      unsigned int hit;
>      int prot;
> -    MemTxAttrs attrs = {};
> +    MemTxAttrs attrs = MEMTXATTRS_CPU(cs);
>  
>      attrs.secure = mb_cpu_access_is_secure(cpu, access_type);
>  
> @@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
>      unsigned int hit;
>  
>      /* Caller doesn't initialize */
> -    *attrs = (MemTxAttrs) {};
> +    *attrs = MEMTXATTRS_CPU(cs);
>      attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD);
>  
>      if (mmu_idx != MMU_NOMMU_IDX) {
> -- 
> 2.34.1
> 


  reply	other threads:[~2022-11-11 19:42 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-11 18:25 [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Alex Bennée
2022-11-11 18:25 ` [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-11-12  4:18   ` Richard Henderson
2022-11-21 18:32   ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Alex Bennée
2022-11-12  5:17   ` Richard Henderson
2022-11-12  5:26   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 03/20] target/arm: ensure HVF traps " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 04/20] target/arm: ensure KVM " Alex Bennée
2022-11-12  5:29   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 05/20] target/arm: ensure m-profile helpers " Alex Bennée
2022-11-12  5:26   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 07/20] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-11-11 18:25 ` [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access Alex Bennée
2022-11-12  5:36   ` Richard Henderson
2022-11-13 19:43   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Alex Bennée
2022-11-11 19:41   ` Edgar E. Iglesias [this message]
2022-11-12  5:37   ` Richard Henderson
2022-11-13 19:44   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 11/20] target/sparc: " Alex Bennée
2022-11-12  1:02   ` Mark Cave-Ayland
2022-11-12  5:38   ` Richard Henderson
2022-11-13 19:45   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 12/20] target/riscv: " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs Alex Bennée
2022-11-12  5:49   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 14/20] hw/audio: explicitly set .requester_type for intel-hda Alex Bennée
2022-11-12  5:50   ` Richard Henderson
2022-11-13 19:50     ` Philippe Mathieu-Daudé
2022-11-21 18:39   ` Peter Maydell
2022-11-21 22:14     ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Alex Bennée
2022-11-12  5:51   ` Richard Henderson
2022-11-13 19:52   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Alex Bennée
2022-11-12  5:52   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Alex Bennée
2022-11-12  5:57   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Alex Bennée
2022-11-12  6:02   ` Richard Henderson
2022-11-21 18:43   ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Alex Bennée
2022-11-12  6:04   ` Richard Henderson
2022-11-13 20:04   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 20/20] include/hw: add commentary to current_cpu export Alex Bennée
2022-11-12  6:05   ` Richard Henderson

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