From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, "Michael Rolnik" <mrolnik@gmail.com>,
"Taylor Simpson" <tsimpson@quicinc.com>,
"Song Gao" <gaosong@loongson.cn>,
"Xiaojuan Yang" <yangxiaojuan@loongson.cn>,
"Laurent Vivier" <laurent@vivier.eu>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Chris Wulff" <crwulff@gmail.com>, "Marek Vasut" <marex@denx.de>,
"Stafford Horne" <shorne@gmail.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Greg Kurz" <groug@kaod.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Artyom Tarasenko" <atar4qemu@gmail.com>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Max Filippov" <jcmvbkbc@gmail.com>,
qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH for-8.0 04/19] target/cris: Convert to 3-phase reset
Date: Thu, 24 Nov 2022 15:44:09 +0100 [thread overview]
Message-ID: <Y3+DOQLB+k4brf+3@toto> (raw)
In-Reply-To: <20221124115023.2437291-5-peter.maydell@linaro.org>
On Thu, Nov 24, 2022 at 11:50:07AM +0000, Peter Maydell wrote:
> Convert the cris CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/cris/cpu-qom.h | 4 ++--
> target/cris/cpu.c | 12 ++++++++----
> 2 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
> index 71e8af0e70a..431a1d536a9 100644
> --- a/target/cris/cpu-qom.h
> +++ b/target/cris/cpu-qom.h
> @@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
> /**
> * CRISCPUClass:
> * @parent_realize: The parent class' realize handler.
> - * @parent_reset: The parent class' reset handler.
> + * @parent_phases: The parent class' reset phase handlers.
> * @vr: Version Register value.
> *
> * A CRIS CPU model.
> @@ -41,7 +41,7 @@ struct CRISCPUClass {
> /*< public >*/
>
> DeviceRealize parent_realize;
> - DeviceReset parent_reset;
> + ResettablePhases parent_phases;
>
> uint32_t vr;
> };
> diff --git a/target/cris/cpu.c b/target/cris/cpu.c
> index fb05dc6f9ab..a6a93c23595 100644
> --- a/target/cris/cpu.c
> +++ b/target/cris/cpu.c
> @@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs)
> return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> }
>
> -static void cris_cpu_reset(DeviceState *dev)
> +static void cris_cpu_reset_hold(Object *obj)
> {
> - CPUState *s = CPU(dev);
> + CPUState *s = CPU(obj);
> CRISCPU *cpu = CRIS_CPU(s);
> CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
> CPUCRISState *env = &cpu->env;
> uint32_t vr;
>
> - ccc->parent_reset(dev);
> + if (ccc->parent_phases.hold) {
> + ccc->parent_phases.hold(obj);
> + }
>
> vr = env->pregs[PR_VR];
> memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
> @@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
> DeviceClass *dc = DEVICE_CLASS(oc);
> CPUClass *cc = CPU_CLASS(oc);
> CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
> + ResettableClass *rc = RESETTABLE_CLASS(oc);
>
> device_class_set_parent_realize(dc, cris_cpu_realizefn,
> &ccc->parent_realize);
>
> - device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);
> + resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL,
> + &ccc->parent_phases);
>
> cc->class_by_name = cris_cpu_class_by_name;
> cc->has_work = cris_cpu_has_work;
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-11-24 14:52 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 11:50 [PATCH for-8.0 00/19] Convert most CPU classes to 3-phase reset Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 01/19] hw/core/cpu-common: Convert TYPE_CPU class " Peter Maydell
2022-11-27 22:30 ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 02/19] target/arm: Convert " Peter Maydell
2022-11-24 15:15 ` Cédric Le Goater
2022-11-27 22:28 ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 03/19] target/avr: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 04/19] target/cris: " Peter Maydell
2022-11-24 14:44 ` Edgar E. Iglesias [this message]
2022-11-24 11:50 ` [PATCH for-8.0 05/19] target/hexagon: " Peter Maydell
2022-11-30 4:38 ` Taylor Simpson
2022-11-24 11:50 ` [PATCH for-8.0 06/19] target/i386: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 07/19] target/loongarch: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 08/19] target/m68k: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 09/19] target/microblaze: " Peter Maydell
2022-11-24 14:44 ` Edgar E. Iglesias
2022-11-24 11:50 ` [PATCH for-8.0 10/19] target/mips: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 11/19] target/nios2: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 12/19] target/openrisc: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 13/19] target/ppc: " Peter Maydell
2022-11-24 15:15 ` Cédric Le Goater
2022-11-24 15:18 ` Greg Kurz
2022-11-24 11:50 ` [PATCH for-8.0 14/19] target/riscv: " Peter Maydell
2022-11-27 22:29 ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 15/19] target/rx: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 16/19] target/sh4: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 17/19] target/sparc: " Peter Maydell
2022-11-30 9:23 ` Mark Cave-Ayland
2022-11-24 11:50 ` [PATCH for-8.0 18/19] target/tricore: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 19/19] target/xtensa: " Peter Maydell
2022-11-24 13:46 ` [PATCH for-8.0 00/19] Convert most CPU classes " Philippe Mathieu-Daudé
2022-11-30 10:51 ` Philippe Mathieu-Daudé
2022-11-30 12:38 ` Peter Maydell
2022-11-30 13:22 ` Philippe Mathieu-Daudé
2022-11-26 15:50 ` Richard Henderson
2022-12-16 16:02 ` Peter Maydell
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