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Iglesias" To: Peter Maydell Cc: qemu-devel@nongnu.org, Michael Rolnik , Taylor Simpson , Song Gao , Xiaojuan Yang , Laurent Vivier , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?iso-8859-1?Q?C=E9dric?= Le Goater , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Bin Meng , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH for-8.0 04/19] target/cris: Convert to 3-phase reset Message-ID: References: <20221124115023.2437291-1-peter.maydell@linaro.org> <20221124115023.2437291-5-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221124115023.2437291-5-peter.maydell@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=edgar.iglesias@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Nov 24, 2022 at 11:50:07AM +0000, Peter Maydell wrote: > Convert the cris CPU class to use 3-phase reset, so it doesn't > need to use device_class_set_parent_reset() any more. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Peter Maydell > --- > target/cris/cpu-qom.h | 4 ++-- > target/cris/cpu.c | 12 ++++++++---- > 2 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h > index 71e8af0e70a..431a1d536a9 100644 > --- a/target/cris/cpu-qom.h > +++ b/target/cris/cpu-qom.h > @@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) > /** > * CRISCPUClass: > * @parent_realize: The parent class' realize handler. > - * @parent_reset: The parent class' reset handler. > + * @parent_phases: The parent class' reset phase handlers. > * @vr: Version Register value. > * > * A CRIS CPU model. > @@ -41,7 +41,7 @@ struct CRISCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - DeviceReset parent_reset; > + ResettablePhases parent_phases; > > uint32_t vr; > }; > diff --git a/target/cris/cpu.c b/target/cris/cpu.c > index fb05dc6f9ab..a6a93c23595 100644 > --- a/target/cris/cpu.c > +++ b/target/cris/cpu.c > @@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs) > return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > } > > -static void cris_cpu_reset(DeviceState *dev) > +static void cris_cpu_reset_hold(Object *obj) > { > - CPUState *s = CPU(dev); > + CPUState *s = CPU(obj); > CRISCPU *cpu = CRIS_CPU(s); > CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); > CPUCRISState *env = &cpu->env; > uint32_t vr; > > - ccc->parent_reset(dev); > + if (ccc->parent_phases.hold) { > + ccc->parent_phases.hold(obj); > + } > > vr = env->pregs[PR_VR]; > memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); > @@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) > DeviceClass *dc = DEVICE_CLASS(oc); > CPUClass *cc = CPU_CLASS(oc); > CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); > + ResettableClass *rc = RESETTABLE_CLASS(oc); > > device_class_set_parent_realize(dc, cris_cpu_realizefn, > &ccc->parent_realize); > > - device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); > + resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL, > + &ccc->parent_phases); > > cc->class_by_name = cris_cpu_class_by_name; > cc->has_work = cris_cpu_has_work; > -- > 2.25.1 >