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[81.232.4.135]) by smtp.gmail.com with ESMTPSA id v14-20020a19740e000000b0048b365176d9sm379457lfe.286.2022.12.13.06.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 06:14:42 -0800 (PST) Date: Tue, 13 Dec 2022 14:54:55 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Cc: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , qemu-devel@nongnu.org, Daniel Henrique Barboza , BALATON Zoltan , Alex =?iso-8859-1?Q?Benn=E9e?= , Alistair Francis , David Gibson , Jason Wang , =?iso-8859-1?Q?C=E9dric?= Le Goater , Greg Kurz , qemu-arm@nongnu.org, qemu-ppc@nongnu.org Subject: Re: [RFC PATCH-for-8.0 3/3] hw/net/xilinx_ethlite: Replace tswap32() by be32_to_cpu() Message-ID: References: <20221213125218.39868-1-philmd@linaro.org> <20221213125218.39868-4-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Dec 13, 2022 at 01:53:15PM +0000, Peter Maydell wrote: > On Tue, 13 Dec 2022 at 12:52, Philippe Mathieu-Daudé wrote: > > > > This partly revert commit d48751ed4f ("xilinx-ethlite: > > Simplify byteswapping to/from brams") which states the > > packet data is stored in big-endian. > > > > Signed-off-by: Philippe Mathieu-Daudé > > > @@ -102,8 +102,8 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) > > D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r)); > > break; > > > > - default: > > - r = tswap32(s->regs[addr]); > > + default: /* Packet data */ > > + r = be32_to_cpu(s->regs[addr]); > > break; > > } > > return r; > > @@ -160,8 +160,8 @@ eth_write(void *opaque, hwaddr addr, > > s->regs[addr] = value; > > break; > > > > - default: > > - s->regs[addr] = tswap32(value); > > + default: /* Packet data */ > > + s->regs[addr] = cpu_to_be32(value); > > break; > > } > > } > > This is a change of behaviour for this device in the > qemu-system-microblazeel petalogix-s3adsp1800 board, because > previously on that system the bytes of the rx buffer would > appear in the registers in little-endian order and now they > will appear in big-endian order. > > Edgar, do you know what the real hardware does here ? > Yeah, I think these tx/rx buffers (the default case with tswap32) should be modelled as plain RAM's (they are just RAM's on real HW). Because we're modeling as MMIO regs, I think we get into endianness trouble when the ethernet output logic treats the content as a blob (thus the need for byteswaps). Does that make sense? Cheers, Edgar