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cujfgurhepfffhvfevuffkfhggtggugfgjsehtkeertddttdejnecuhfhrohhmpefrvght vghrucffvghlvghvohhrhigrshcuoehpvghtvghrsehpjhgurdguvghvqeenucggtffrrg htthgvrhhnpeeuteekfffgtdegveefveduteelgfduteffvdffveejlefffeehffffleel iedtgeenucffohhmrghinhepghhithhhuhgsrdgtohhmnecuvehluhhsthgvrhfuihiivg eptdenucfrrghrrghmpehmrghilhhfrhhomhepphgvthgvrhesphhjugdruggvvh X-ME-Proxy: Feedback-ID: i9e814621:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Dec 2022 15:23:44 -0500 (EST) Date: Fri, 30 Dec 2022 12:23:41 -0800 From: Peter Delevoryas To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Steven Lee , Peter Delevoryas , qemu-arm@nongnu.org, Cleber Rosa , Peter Maydell , Beraldo Leal , Wainer dos Santos Moschetta , Troy Lee , Andrew Jeffery , Joel Stanley , =?iso-8859-1?Q?C=E9dric?= Le Goater , Peter Delevoryas , Jamin Lin Subject: Re: [PATCH 6/9] hw/arm/aspeed_ast10x0: Map HACE peripheral Message-ID: References: <20221229152325.32041-1-philmd@linaro.org> <20221229152325.32041-7-philmd@linaro.org> <9de13ab3-beb6-a86e-5eb3-b4606b0f5b9b@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9de13ab3-beb6-a86e-5eb3-b4606b0f5b9b@linaro.org> Received-SPF: pass client-ip=66.111.4.25; envelope-from=peter@pjd.dev; helo=out1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 30, 2022 at 09:13:29AM +0100, Philippe Mathieu-Daudé wrote: > On 29/12/22 21:52, Peter Delevoryas wrote: > > On Thu, Dec 29, 2022 at 04:23:22PM +0100, Philippe Mathieu-Daudé wrote: > > > Since I don't have access to the datasheet, the relevant > > > values were found in: > > > https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi > > > > > > Before on Zephyr: > > > > > > uart:~$ crypto aes256_cbc_vault > > > aes256_cbc vault key 1 > > > [00:00:06.699,000] hace_global: aspeed_crypto_session_setup > > > [00:00:06.699,000] hace_global: data->cmd: 1c2098 > > > [00:00:06.699,000] hace_global: crypto_data_src: 93340 > > > [00:00:06.699,000] hace_global: crypto_data_dst: 93348 > > > [00:00:06.699,000] hace_global: crypto_ctx_base: 93300 > > > [00:00:06.699,000] hace_global: crypto_data_len: 80000040 > > > [00:00:06.699,000] hace_global: crypto_cmd_reg: 11c2098 > > > [00:00:09.743,000] hace_global: HACE_STS: 0 > > > [00:00:09.743,000] hace_global: HACE poll timeout > > > [00:00:09.743,000] crypto: CBC mode ENCRYPT - Failed > > > [00:00:09.743,000] hace_global: aspeed_crypto_session_free > > > uart:~$ > > > > > > After: > > > > > > uart:~$ crypto aes256_cbc_vault > > > aes256_cbc vault key 1 > > > Was waiting for: > > > 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a > > > ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51 > > > 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef > > > f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10 > > > > > > But got: > > > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > > > > > [00:00:05.771,000] hace_global: aspeed_crypto_session_setup > > > [00:00:05.772,000] hace_global: data->cmd: 1c2098 > > > [00:00:05.772,000] hace_global: crypto_data_src: 93340 > > > [00:00:05.772,000] hace_global: crypto_data_dst: 93348 > > > [00:00:05.772,000] hace_global: crypto_ctx_base: 93300 > > > [00:00:05.772,000] hace_global: crypto_data_len: 80000040 > > > [00:00:05.772,000] hace_global: crypto_cmd_reg: 11c2098 > > > [00:00:05.772,000] hace_global: HACE_STS: 1000 > > > [00:00:05.772,000] crypto: Output length (encryption): 80 > > > [00:00:05.772,000] hace_global: aspeed_crypto_session_free > > > [00:00:05.772,000] hace_global: aspeed_crypto_session_setup > > > [00:00:05.772,000] hace_global: data->cmd: 1c2018 > > > [00:00:05.772,000] hace_global: crypto_data_src: 93340 > > > [00:00:05.772,000] hace_global: crypto_data_dst: 93348 > > > [00:00:05.772,000] hace_global: crypto_ctx_base: 93300 > > > [00:00:05.772,000] hace_global: crypto_data_len: 80000040 > > > [00:00:05.772,000] hace_global: crypto_cmd_reg: 11c2018 > > > [00:00:05.772,000] hace_global: HACE_STS: 1000 > > > [00:00:05.772,000] crypto: Output length (decryption): 64 > > > [00:00:05.772,000] crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text > > > [00:00:05.774,000] hace_global: aspeed_crypto_session_free > > > uart:~$ > > > > > > Signed-off-by: Philippe Mathieu-Daudé > > > > Awesome! > > > > Reviewed-by: Peter Delevoryas > > > > > --- > > > Should we rename HACE 'dram' as 'secram' / 'secure-ram'? > > > > Sure, sounds good to me. > > > > > --- > > > hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++ > > > 1 file changed, 15 insertions(+) > > > > > > diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c > > > index 21a2e62345..02636705b6 100644 > > > --- a/hw/arm/aspeed_ast10x0.c > > > +++ b/hw/arm/aspeed_ast10x0.c > > > @@ -29,6 +29,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { > > > [ASPEED_DEV_SPI1] = 0x7E630000, > > > [ASPEED_DEV_SPI2] = 0x7E640000, > > > [ASPEED_DEV_UDC] = 0x7E6A2000, > > > + [ASPEED_DEV_HACE] = 0x7E6D0000, > > > [ASPEED_DEV_SCU] = 0x7E6E2000, > > > [ASPEED_DEV_JTAG0] = 0x7E6E4000, > > > [ASPEED_DEV_JTAG1] = 0x7E6E4100, > > > @@ -166,6 +167,9 @@ static void aspeed_soc_ast1030_init(Object *obj) > > > snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); > > > object_initialize_child(obj, "gpio", &s->gpio, typename); > > > + snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); > > > + object_initialize_child(obj, "hace", &s->hace, typename); > > > + > > > object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); > > > object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, > > > TYPE_UNIMPLEMENTED_DEVICE); > > > @@ -359,6 +363,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) > > > } > > > aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); > > > + /* HACE */ > > > + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->secsram), > > We need to link the SRAM here, not the sec-SRAM. Nice catch 😅 > > Doing so the hash test works: > > uart:~$ hash test > sha256_test > tv[0]:PASS > tv[1]:PASS > tv[2]:PASS > tv[3]:PASS > tv[4]:PASS > sha384_test > tv[0]:PASS > tv[1]:PASS > tv[2]:PASS > tv[3]:PASS > tv[4]:PASS > tv[5]:PASS > sha512_test > tv[0]:PASS > tv[1]:PASS > tv[2]:PASS > tv[3]:PASS > tv[4]:PASS > tv[5]:PASS > uart:~$ > > rsa / aes256_cbc tests still fail. > Oh nice!!