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Thu, 19 Jan 2023 03:02:17 -0500 (EST) Date: Thu, 19 Jan 2023 09:02:15 +0100 From: Klaus Jensen To: Keith Busch Cc: Alistair Francis , Peter Maydell , Guenter Roeck , Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-nvme@lists.infradead.org, qemu-block@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: completion timeouts with pin-based interrupts in QEMU hw/nvme Message-ID: References: <20230117192115.GA2958104@roeck-us.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="W4BUVAsMEMdcmc71" Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --W4BUVAsMEMdcmc71 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Jan 19 08:28, Klaus Jensen wrote: > On Jan 18 21:03, Keith Busch wrote: > > On Thu, Jan 19, 2023 at 01:10:57PM +1000, Alistair Francis wrote: > > > On Thu, Jan 19, 2023 at 12:44 PM Keith Busch wrot= e: > > > > > > > > Further up, it says the "interrupt gateway" is responsible for > > > > forwarding new interrupt requests while the level remains asserted,= but > > > > it doesn't look like anything is handling that, which essentially t= urns > > > > this into an edge interrupt. Am I missing something, or is this rea= lly > > > > not being handled? > > >=20 > > > Yeah, that wouldn't be handled. In QEMU the PLIC relies on QEMUs > > > internal GPIO lines to trigger an interrupt. So with the current setup > > > we only support edge triggered interrupts. > >=20 > > Thanks for confirming! > >=20 > > Klaus, > > I think we can justify introducing a work-around in the emulated device > > now. My previous proposal with pci_irq_pulse() is no good since it does > > assert+deassert, but it needs to be the other way around, so please > > don't considert that one. > >=20 > > Also, we ought to revisit the intms/intmc usage in the linux driver for > > threaded interrupts. >=20 > +CC: qemu-riscv >=20 > Keith, >=20 > Thanks for digging into this! >=20 > Yeah, you are probably right that we should only use the intms/intmc > changes in the use_threaded_interrupts case, not in general. While my > RFC patch does seem to "fix" this, it is just a workaround as your > analysis indicate. +CC: Philippe, I am observing these timeouts/aborts on mips as well, so I guess that emulation could suffer from the same issue? --W4BUVAsMEMdcmc71 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmPI+QYACgkQTeGvMW1P DekHAwf+Ki1LlCBgmoe95m0vajU7TuDu1kMglgpZ9t7UsBwGa88syocxbt0Xbgi8 9EvIPkncL1hlzzimo/tFa4Ukr5qiCucctT9xW37x2EWpMOk8Dv1Vo3W0pC9X6Apx nASE5/LGq/hH1IhnewMKPwABXfpd/OCiNnlkbYtp7dQhk9Yls3WoyASZVnXAKk4P Gu8nsBRUutZT1VEjOIv8GYwQwaJ5IHEWULTndsiQZge/vWKgHLev3xDfOtKXKsmw mhZm9n1CUZBH2dF9hZCfxGqp1TpWZXKuH5rpw3wcLOFShd8CznI7PvtqNodfeVTo fveeCWF7UH05j2gpTGQjY1wKLvjxbA== =ZriN -----END PGP SIGNATURE----- --W4BUVAsMEMdcmc71--