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[35.247.111.240]) by smtp.gmail.com with ESMTPSA id s184sm3899562pgc.29.2021.05.04.09.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 09:20:16 -0700 (PDT) Date: Tue, 4 May 2021 16:20:13 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Yang Zhong , qemu-devel@nongnu.org, kai.huang@intel.com Subject: Re: [RESEND PATCH 05/32] vl: Add "sgx-epc" option to expose SGX EPC sections to guest Message-ID: References: <20210430062455.8117-1-yang.zhong@intel.com> <20210430062455.8117-6-yang.zhong@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=seanjc@google.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, May 04, 2021, Paolo Bonzini wrote: > On 04/05/21 02:09, Sean Christopherson wrote: > > Is there a way to process "-device sgx-epc..." before vCPUs are realized? The > > ordering problem was the only reason I added a dedicated option. > > If it's just CPUID, one possibility could be to mark the EPC sections > specially in KVM_SET_USER_MEMORY_REGION and synthesize the leaves within > KVM; or even look inside the VMA structs and detect EPC regions that way. I experimented with those options, and a few others, and they all lack the flexibility of making EPC just another memory backend. For synthesizing CPUID within KVM: - Requires a vendor specific memory region flag for all architectures to work around a quirk of one userspace VMM. - Pushes a lot of complexity into KVM, e.g. KVM needs to update CPUID in response to memslot changes, and needs to query memslots in response to CPUID changes. - Does KVM or userspace define the section attributes, e.g. confidentiality, integrity, etc...? If KVM, are they hardcoded to match the host? What happens if a future Intel platform supports multiple EPC sections with different attributes? If userspace, how does userspace communicate the attributes? - How does userspace know what KVM enumerated to the guest? See the whole KVM_GET_CPUID2 fiasco... - Prevents userspace from enumerating EPC without a memslot, e.g. to trap on the first EPC access for tracking purposes. For probing VMAs: - In addition to the above issues, requires MMU notifier integration to update CPUID in response to a VMA change. - Requires SGX subsystem to provide a helper to identify EPC VMAs. In short, I feel very strongly that this is QEMU's problem to solve. > Otherwise, the -M solution would work. > > Paolo > > > From the changelog: > > > > Because SGX EPC is enumerated through CPUID, EPC "devices" need to be > > realized prior to realizing the vCPUs themselves, i.e. long before > > generic devices are parsed and realized. > > > > So even though EPC sections could be realized through the generic > > -devices command, they need to be created much earlier for them to > > actually be usable by the guest. >