From: David Gibson <david@gibson.dropbear.id.au>
To: matheus.ferst@eldorado.org.br
Cc: richard.henderson@linaro.org, qemu-devel@nongnu.org,
f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org,
lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br
Subject: Re: [PATCH v4 02/31] target/ppc: Split out decode_legacy
Date: Thu, 13 May 2021 14:03:48 +1000 [thread overview]
Message-ID: <YJylJHMKdbXbbfzE@yekko> (raw)
In-Reply-To: <20210512185441.3619828-3-matheus.ferst@eldorado.org.br>
[-- Attachment #1: Type: text/plain, Size: 6415 bytes --]
On Wed, May 12, 2021 at 03:54:12PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1.
> ---
> target/ppc/translate.c | 115 +++++++++++++++++++++++------------------
> 1 file changed, 64 insertions(+), 51 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 9abe03222d..3ad4c7163d 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9253,6 +9253,62 @@ void ppc_cpu_dump_statistics(CPUState *cs, int flags)
> #endif
> }
>
> +static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
> +{
> + opc_handler_t **table, *handler;
> + uint32_t inval;
> +
> + ctx->opcode = insn;
> +
> + LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
> + insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
> + ctx->le_mode ? "little" : "big");
> +
> + table = cpu->opcodes;
> + handler = table[opc1(insn)];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + handler = table[opc2(insn)];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + handler = table[opc3(insn)];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + handler = table[opc4(insn)];
> + }
> + }
> + }
> +
> + /* Is opcode *REALLY* valid ? */
> + if (unlikely(handler->handler == &gen_invalid)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
> + "%02x - %02x - %02x - %02x (%08x) "
> + TARGET_FMT_lx "\n",
> + opc1(insn), opc2(insn), opc3(insn), opc4(insn),
> + insn, ctx->cia);
> + return false;
> + }
> +
> + if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
> + && Rc(insn))) {
> + inval = handler->inval2;
> + } else {
> + inval = handler->inval1;
> + }
> +
> + if (unlikely((insn & inval) != 0)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
> + "%02x - %02x - %02x - %02x (%08x) "
> + TARGET_FMT_lx "\n", insn & inval,
> + opc1(insn), opc2(insn), opc3(insn), opc4(insn),
> + insn, ctx->cia);
> + return false;
> + }
> +
> + handler->handler(ctx);
> + return true;
> +}
> +
> static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> @@ -9334,66 +9390,23 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = cs->env_ptr;
> - opc_handler_t **table, *handler;
> + uint32_t insn;
> + bool ok;
>
> LOG_DISAS("----------------\n");
> LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
> ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
>
> ctx->cia = ctx->base.pc_next;
> - ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
> - need_byteswap(ctx));
> -
> - LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
> - ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->le_mode ? "little" : "big");
> + insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
> ctx->base.pc_next += 4;
> - table = cpu->opcodes;
> - handler = table[opc1(ctx->opcode)];
> - if (is_indirect_opcode(handler)) {
> - table = ind_table(handler);
> - handler = table[opc2(ctx->opcode)];
> - if (is_indirect_opcode(handler)) {
> - table = ind_table(handler);
> - handler = table[opc3(ctx->opcode)];
> - if (is_indirect_opcode(handler)) {
> - table = ind_table(handler);
> - handler = table[opc4(ctx->opcode)];
> - }
> - }
> - }
> - /* Is opcode *REALLY* valid ? */
> - if (unlikely(handler->handler == &gen_invalid)) {
> - qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
> - "%02x - %02x - %02x - %02x (%08x) "
> - TARGET_FMT_lx " %d\n",
> - opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->cia, (int)msr_ir);
> - } else {
> - uint32_t inval;
>
> - if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
> - && Rc(ctx->opcode))) {
> - inval = handler->inval2;
> - } else {
> - inval = handler->inval1;
> - }
> -
> - if (unlikely((ctx->opcode & inval) != 0)) {
> - qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
> - "%02x - %02x - %02x - %02x (%08x) "
> - TARGET_FMT_lx "\n", ctx->opcode & inval,
> - opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->cia);
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> - ctx->base.is_jmp = DISAS_NORETURN;
> - return;
> - }
> + ok = decode_legacy(cpu, ctx, insn);
> + if (!ok) {
> + gen_invalid(ctx);
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
> - (*(handler->handler))(ctx);
> +
> #if defined(DO_PPC_STATISTICS)
> handler->count++;
> #endif
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-05-13 4:34 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
2021-05-13 4:03 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
2021-05-13 4:03 ` David Gibson [this message]
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
2021-05-13 4:06 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
2021-05-13 4:06 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
2021-05-13 4:07 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
2021-05-13 4:08 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
2021-05-13 4:10 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
2021-05-12 19:31 ` Bruno Piazera Larsen
2021-05-13 4:11 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
2021-05-13 4:12 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-12 19:21 ` Matheus K. Ferst
2021-05-13 4:14 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-12 18:54 ` [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-12 18:54 ` [PATCH v4 13/31] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-12 18:54 ` [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-12 18:54 ` [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-12 18:54 ` [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-12 19:45 ` Bruno Piazera Larsen
2021-05-12 18:54 ` [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-12 18:54 ` [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
2021-05-13 10:37 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
2021-05-13 10:42 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-13 10:50 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-13 11:01 ` Richard Henderson
2021-05-13 11:43 ` Matheus K. Ferst
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-13 11:31 ` Richard Henderson
2021-05-13 12:24 ` Matheus K. Ferst
2021-05-14 0:01 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-13 11:36 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-13 11:40 ` Richard Henderson
2021-05-13 4:22 ` [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions David Gibson
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