From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC5CC433ED for ; Mon, 17 May 2021 06:29:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6BB3E61209 for ; Mon, 17 May 2021 06:29:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6BB3E61209 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1liWkP-0004BW-IF for qemu-devel@archiver.kernel.org; Mon, 17 May 2021 02:29:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1liWfm-0000eG-9E; Mon, 17 May 2021 02:24:15 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:40431 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1liWfj-0005q0-6w; Mon, 17 May 2021 02:24:13 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4Fk8Gr3YLfz9sWQ; Mon, 17 May 2021 16:24:04 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1621232644; bh=8AFTuyHqGyZ4EeHrWbi7hbrcrzo7ONqzGgD2zmCQSCA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ZI+xkCQv5gt7KKSB8UNjGUWApDyS7CYzYiXDpYSEi3isuvsDarWLah16CFCk0vjuS Se1VXHQeSQ9Clv+e7rqwKn11Dkq/gR1M3gzNiicgo7W0gghU1inVSLzUlMj3tUuZgh y53w8Vz35C82pdPCuPyBGhbV16FsqiEycr1kTx3w= Date: Mon, 17 May 2021 15:39:35 +1000 From: David Gibson To: Nicholas Piggin Subject: Re: [PATCH] target/ppc: Implement ISA v3.1 wait variants Message-ID: References: <20210517024651.2200837-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="8CvYUvMj9aFFhOMQ" Content-Disposition: inline In-Reply-To: <20210517024651.2200837-1-npiggin@gmail.com> Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --8CvYUvMj9aFFhOMQ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, May 17, 2021 at 12:46:51PM +1000, Nicholas Piggin wrote: > ISA v3.1 adds new variations of wait, specified by the WC field. These > are not compatible with the wait 0 implementation, because they add > additional conditions that cause the processor to resume, which can > cause software to hang or run very slowly. >=20 > Add the new wait variants with a trivial no-op implementation, which is > allowed, as explained in comments: software must not depend on any > particular architected WC condition having caused resumption of > execution, therefore a no-op implementation is architecturally correct. >=20 > Signed-off-by: Nicholas Piggin Logic looks fine. There is no test on the CPU's features or model here, though, so this will change behaviour for pre-3.1 CPUs as well. What would invoking these wait variants (presumably reserved) on earlier CPUs do? > --- > Implementing cpu_relax() in Linux with wait 2,0 (pause_short) causes a > hang on boot without this patch. >=20 > target/ppc/translate.c | 39 +++++++++++++++++++++++++++++++++------ > 1 file changed, 33 insertions(+), 6 deletions(-) >=20 > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index a6381208a5..80db450cab 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -3619,12 +3619,39 @@ static void gen_sync(DisasContext *ctx) > /* wait */ > static void gen_wait(DisasContext *ctx) > { > - TCGv_i32 t0 =3D tcg_const_i32(1); > - tcg_gen_st_i32(t0, cpu_env, > - -offsetof(PowerPCCPU, env) + offsetof(CPUState, halte= d)); > - tcg_temp_free_i32(t0); > - /* Stop translation, as the CPU is supposed to sleep from now */ > - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > + uint32_t wc =3D (ctx->opcode >> 21) & 3; > + > + /* > + * wait 0 waits for an exception to occur. > + */ > + if (wc =3D=3D 0) { > + TCGv_i32 t0 =3D tcg_const_i32(1); > + tcg_gen_st_i32(t0, cpu_env, > + -offsetof(PowerPCCPU, env) + offsetof(CPUState, h= alted)); > + tcg_temp_free_i32(t0); > + /* Stop translation, as the CPU is supposed to sleep from now */ > + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); > + } > + > + /* > + * Other wait types must not wait until an exception occurs because > + * ignoring their other wake-up conditions could cause a hang. > + * > + * wait 1 (waitrsv) waits for an exception or a reservation to be lo= st. > + * This can happen for implementation specific reasons, so it can be > + * implemented as a no-op. > + * > + * wait 2 waits for an exception or an amount of time to pass. This = is > + * implementation specific so it can be implemented as a no-op. > + * > + * wait 3 is reserved, so it may be implemented as a no-op. > + * > + * ISA v3.1 does allow for execution to resume "in the rare case of > + * an implementation-dependent event", so in any case software must > + * not depend on the architected resumption condition to become > + * true, so no-op implementations are architecturally correct (if > + * suboptimal). > + */ > } > =20 > #if defined(TARGET_PPC64) --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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