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From: David Gibson <david@gibson.dropbear.id.au>
To: matheus.ferst@eldorado.org.br
Cc: richard.henderson@linaro.org, qemu-devel@nongnu.org,
	f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org,
	lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br
Subject: Re: [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
Date: Tue, 18 May 2021 10:14:42 +1000	[thread overview]
Message-ID: <YKMG8hpwPw+MYaaj@yekko> (raw)
In-Reply-To: <20210517205025.3777947-3-matheus.ferst@eldorado.org.br>

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On Mon, May 17, 2021 at 05:50:04PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
> 
> Remove the synthetic "exception" after no more uses.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>

Applied to ppc-for-6.1, thanks.

> ---
>  linux-user/ppc/cpu_loop.c |  3 ---
>  target/ppc/cpu.h          |  1 -
>  target/ppc/translate.c    | 24 +++++++-----------------
>  3 files changed, 7 insertions(+), 21 deletions(-)
> 
> diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
> index 4a0f6c8dc2..fe526693d2 100644
> --- a/linux-user/ppc/cpu_loop.c
> +++ b/linux-user/ppc/cpu_loop.c
> @@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
>              cpu_abort(cs, "Maintenance exception while in user mode. "
>                        "Aborting\n");
>              break;
> -        case POWERPC_EXCP_STOP:     /* stop translation                      */
> -            /* We did invalidate the instruction cache. Go on */
> -            break;
>          case POWERPC_EXCP_BRANCH:   /* branch instruction:                   */
>              /* We just stopped because of a branch. Go on */
>              break;
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 99ee1e09b2..9e38df685d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -132,7 +132,6 @@ enum {
>      /* EOL                                                                   */
>      POWERPC_EXCP_NB       = 103,
>      /* QEMU exceptions: used internally during code translation              */
> -    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
>      POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
>      /* QEMU exceptions: special cases we want to stop translation            */
>      POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 060ef83bc0..f57b67be5f 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -369,13 +369,6 @@ static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
>      gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
>  }
>  
> -/* Stop translation */
> -static inline void gen_stop_exception(DisasContext *ctx)
> -{
> -    gen_update_nip(ctx, ctx->base.pc_next);
> -    ctx->exception = POWERPC_EXCP_STOP;
> -}
> -
>  /*****************************************************************************/
>  /* SPR READ/WRITE CALLBACKS */
>  
> @@ -829,7 +822,7 @@ void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
>  {
>      gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
>      /* Must stop the translation as endianness may have changed */
> -    gen_stop_exception(ctx);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>  }
>  #endif
>  
> @@ -877,7 +870,7 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
>      gen_store_spr(sprn, cpu_gpr[gprn]);
>      gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
>      /* We must stop translation as we may have rebooted */
> -    gen_stop_exception(ctx);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>  }
>  
>  void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> @@ -4080,7 +4073,7 @@ static void gen_isync(DisasContext *ctx)
>          gen_check_tlb_flush(ctx, false);
>      }
>      tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> -    gen_stop_exception(ctx);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>  }
>  
>  #define MEMOP_GET_SIZE(x)  (1 << ((x) & MO_SIZE))
> @@ -5312,7 +5305,7 @@ static void gen_mtmsrd(DisasContext *ctx)
>          gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
>      }
>      /* Must stop the translation as machine state (may have) changed */
> -    gen_stop_exception(ctx);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>  #endif /* !defined(CONFIG_USER_ONLY) */
>  }
>  #endif /* defined(TARGET_PPC64) */
> @@ -5355,7 +5348,7 @@ static void gen_mtmsr(DisasContext *ctx)
>          tcg_temp_free(msr);
>      }
>      /* Must stop the translation as machine state (may have) changed */
> -    gen_stop_exception(ctx);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>  #endif
>  }
>  
> @@ -7492,7 +7485,7 @@ static void gen_wrtee(DisasContext *ctx)
>       * Stop translation to have a chance to raise an exception if we
>       * just set msr_ee to 1
>       */
> -    gen_stop_exception(ctx);
> +    ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>  #endif /* defined(CONFIG_USER_ONLY) */
>  }
>  
> @@ -7506,7 +7499,7 @@ static void gen_wrteei(DisasContext *ctx)
>      if (ctx->opcode & 0x00008000) {
>          tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
>          /* Stop translation to have a chance to raise an exception */
> -        gen_stop_exception(ctx);
> +        ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>      } else {
>          tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
>      }
> @@ -9128,9 +9121,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
>          case POWERPC_EXCP_BRANCH:
>              ctx->base.is_jmp = DISAS_NORETURN;
>              break;
> -        case POWERPC_EXCP_STOP:
> -            ctx->base.is_jmp = DISAS_EXIT;
> -            break;
>          default:
>              /* Every other ctx->exception should have set NORETURN. */
>              g_assert_not_reached();

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2021-05-18  1:37 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-18  0:13   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-18  0:14   ` David Gibson [this message]
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-18  0:15   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-18  0:17   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-18  0:19   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-18  0:19   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-18  0:20   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-18  0:20   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-18  0:21   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-18  0:23   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-18  0:25   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-18  0:35   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
2021-05-18  0:36   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
2021-05-18  0:37   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-18  0:44   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-18  0:45   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-18  0:47   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-18  0:47   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-18  0:49   ` David Gibson
2021-05-18  9:48   ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-18  0:51   ` David Gibson
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-18  0:52   ` David Gibson
2021-05-18  9:54   ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-18  0:53   ` David Gibson
2021-05-18  9:55   ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18  0:56   ` David Gibson
2021-05-18 10:12   ` Richard Henderson
2021-05-21 17:25     ` Matheus K. Ferst
2021-05-24 18:51       ` Richard Henderson
2021-05-26 15:17         ` Matheus K. Ferst
2021-05-26 16:11           ` Richard Henderson
2021-05-27  1:11           ` David Gibson
2021-05-18  3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson

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