From: David Gibson <david@gibson.dropbear.id.au>
To: matheus.ferst@eldorado.org.br
Cc: richard.henderson@linaro.org, qemu-devel@nongnu.org,
f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org,
lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br
Subject: Re: [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start
Date: Tue, 18 May 2021 10:13:49 +1000 [thread overview]
Message-ID: <YKMGvSajoZtoc1m4@yekko> (raw)
In-Reply-To: <20210517205025.3777947-2-matheus.ferst@eldorado.org.br>
[-- Attachment #1: Type: text/plain, Size: 12297 bytes --]
On Mon, May 17, 2021 at 05:50:03PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Create a function to handle the details for interacting with icount.
>
> Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
> to the next tb, where the code emitted for gen_tb_start() will
> determine if we must exit. We can thus remove any matching
> conditional call to gen_stop_exception.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 174 +++++++++--------------------------------
> 1 file changed, 39 insertions(+), 135 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d51a1913a7..060ef83bc0 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -304,6 +304,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> +static void gen_icount_io_start(DisasContext *ctx)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + /*
> + * An I/O instruction must be last in the TB.
> + * Chain to the next TB, and let the code from gen_tb_start
> + * decide if we need to return to the main loop.
> + * Doing this first also allows this value to be overridden.
> + */
> + ctx->base.is_jmp = DISAS_TOO_MANY;
> + }
> +}
> +
> /*
> * Tells the caller what is the appropriate exception to generate and prepares
> * SPR registers for this exception.
> @@ -540,24 +554,14 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> #if !defined(CONFIG_USER_ONLY)
> void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> #endif
>
> @@ -565,24 +569,14 @@ void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> /* Time base */
> void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
> @@ -598,24 +592,14 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> #if !defined(CONFIG_USER_ONLY)
> void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
> @@ -631,80 +615,45 @@ void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> #if defined(TARGET_PPC64)
> void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> /* HDECR */
> void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> #endif
> @@ -912,71 +861,41 @@ void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> #if !defined(CONFIG_USER_ONLY)
> void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_store_spr(sprn, cpu_gpr[gprn]);
> gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> /* We must stop translation as we may have rebooted */
> gen_stop_exception(ctx);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> #endif
>
> @@ -2860,18 +2779,13 @@ static void gen_darn(DisasContext *ctx)
> if (l > 2) {
> tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
> } else {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (l == 0) {
> gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
> } else {
> /* Return 64-bit random for both CRN and RRN */
> gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
> }
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> }
> #endif
> @@ -5013,9 +4927,7 @@ static void gen_rfi(DisasContext *ctx)
> }
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5030,9 +4942,7 @@ static void gen_rfid(DisasContext *ctx)
> #else
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5047,9 +4957,7 @@ static void gen_rfscv(DisasContext *ctx)
> #else
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5379,9 +5287,7 @@ static void gen_mtmsrd(DisasContext *ctx)
> CHK_SV;
>
> #if !defined(CONFIG_USER_ONLY)
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (ctx->opcode & 0x00010000) {
> /* L=1 form only updates EE and RI */
> TCGv t0 = tcg_temp_new();
> @@ -5416,9 +5322,7 @@ static void gen_mtmsr(DisasContext *ctx)
> CHK_SV;
>
> #if !defined(CONFIG_USER_ONLY)
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (ctx->opcode & 0x00010000) {
> /* L=1 form only updates EE and RI */
> TCGv t0 = tcg_temp_new();
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-05-18 1:40 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-18 0:13 ` David Gibson [this message]
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-18 0:14 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-18 0:15 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-18 0:17 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-18 0:21 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-18 0:23 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-18 0:25 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-18 0:35 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
2021-05-18 0:36 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
2021-05-18 0:37 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-18 0:44 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-18 0:45 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-18 0:49 ` David Gibson
2021-05-18 9:48 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-18 0:51 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-18 0:52 ` David Gibson
2021-05-18 9:54 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-18 0:53 ` David Gibson
2021-05-18 9:55 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18 0:56 ` David Gibson
2021-05-18 10:12 ` Richard Henderson
2021-05-21 17:25 ` Matheus K. Ferst
2021-05-24 18:51 ` Richard Henderson
2021-05-26 15:17 ` Matheus K. Ferst
2021-05-26 16:11 ` Richard Henderson
2021-05-27 1:11 ` David Gibson
2021-05-18 3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson
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