From: David Gibson <david@gibson.dropbear.id.au>
To: matheus.ferst@eldorado.org.br
Cc: richard.henderson@linaro.org, qemu-devel@nongnu.org,
f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org,
lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br
Subject: Re: [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree
Date: Tue, 18 May 2021 10:47:18 +1000 [thread overview]
Message-ID: <YKMOlqswrXMY2ssN@yekko> (raw)
In-Reply-To: <20210517205025.3777947-18-matheus.ferst@eldorado.org.br>
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On Mon, May 17, 2021 at 05:50:19PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> These are all connected by macros in the legacy decoding.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 22 ++++++
> target/ppc/translate.c | 85 +---------------------
> target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++
> 3 files changed, 49 insertions(+), 82 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 70f64c235b..00ec0f4328 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
> LDX 011111 ..... ..... ..... 0000010101 - @X
> LDUX 011111 ..... ..... ..... 0000110101 - @X
>
> +### Fixed-Point Store Instructions
> +
> +STB 100110 ..... ..... ................ @D
> +STBU 100111 ..... ..... ................ @D
> +STBX 011111 ..... ..... ..... 0011010111 - @X
> +STBUX 011111 ..... ..... ..... 0011110111 - @X
> +
> +STH 101100 ..... ..... ................ @D
> +STHU 101101 ..... ..... ................ @D
> +STHX 011111 ..... ..... ..... 0110010111 - @X
> +STHUX 011111 ..... ..... ..... 0110110111 - @X
> +
> +STW 100100 ..... ..... ................ @D
> +STWU 100101 ..... ..... ................ @D
> +STWX 011111 ..... ..... ..... 0010010111 - @X
> +STWUX 011111 ..... ..... ..... 0010110111 - @X
> +
> +STD 111110 ..... ..... ..............00 @DS
> +STDU 111110 ..... ..... ..............01 @DS
> +STDX 011111 ..... ..... ..... 0010010101 - @X
> +STDUX 011111 ..... ..... ..... 0010110101 - @X
> +
> ### Fixed-Point Arithmetic Instructions
>
> ADDI 001110 ..... ..... ................ @D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index e037efcfe1..bf624edba6 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3385,7 +3385,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
> tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
> }
>
> +#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
> GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
> +#endif
> GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
> GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
>
> @@ -3518,52 +3520,6 @@ static void gen_lq(DisasContext *ctx)
> #endif
>
> /*** Integer store ***/
> -#define GEN_ST(name, stop, opc, type) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> -#define GEN_STU(name, stop, opc, type) \
> -static void glue(gen_, stop##u)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - if (type == PPC_64B) \
> - gen_addr_imm_index(ctx, EA, 0x03); \
> - else \
> - gen_addr_imm_index(ctx, EA, 0); \
> - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> -#define GEN_STUX(name, stop, opc2, opc3, type) \
> -static void glue(gen_, name##ux)(DisasContext *ctx) \
> -{ \
> - TCGv EA; \
> - if (unlikely(rA(ctx->opcode) == 0)) { \
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
> - return; \
> - } \
> - gen_set_access_type(ctx, ACCESS_INT); \
> - EA = tcg_temp_new(); \
> - gen_addr_reg_index(ctx, EA); \
> - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
> - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
> - tcg_temp_free(EA); \
> -}
> -
> #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
> static void glue(gen_, name##x)(DisasContext *ctx) \
> { \
> @@ -3581,19 +3537,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
> #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
> GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
>
> -#define GEN_STS(name, stop, op, type) \
> -GEN_ST(name, stop, op | 0x20, type); \
> -GEN_STU(name, stop, op | 0x21, type); \
> -GEN_STUX(name, stop, 0x17, op | 0x01, type); \
> -GEN_STX(name, stop, 0x17, op | 0x00, type)
> -
> -/* stb stbu stbux stbx */
> -GEN_STS(stb, st8, 0x06, PPC_INTEGER);
> -/* sth sthu sthux sthx */
> -GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
> -/* stw stwu stwux stwx */
> -GEN_STS(stw, st32, 0x04, PPC_INTEGER);
> -
> #define GEN_STEPX(name, stop, opc2, opc3) \
> static void glue(gen_, name##epx)(DisasContext *ctx) \
> { \
> @@ -3615,8 +3558,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
> #endif
>
> #if defined(TARGET_PPC64)
> -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
> -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
> GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
> GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
> GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
> @@ -8252,31 +8193,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
> GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
> #endif
>
> -#undef GEN_ST
> -#undef GEN_STU
> -#undef GEN_STUX
> #undef GEN_STX_E
> -#undef GEN_STS
> -#define GEN_ST(name, stop, opc, type) \
> -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_STU(name, stop, opc, type) \
> -GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
> -#define GEN_STUX(name, stop, opc2, opc3, type) \
> -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
> #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
> GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
> -#define GEN_STS(name, stop, op, type) \
> -GEN_ST(name, stop, op | 0x20, type) \
> -GEN_STU(name, stop, op | 0x21, type) \
> -GEN_STUX(name, stop, 0x17, op | 0x01, type) \
> -GEN_STX(name, stop, 0x17, op | 0x00, type)
> -
> -GEN_STS(stb, st8, 0x06, PPC_INTEGER)
> -GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
> -GEN_STS(stw, st32, 0x04, PPC_INTEGER)
> +
> #if defined(TARGET_PPC64)
> -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
> -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
> GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
> GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
> GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 7687f31d6f..adeee33289 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
> TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
> TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
>
> +/* Store Byte */
> +TRANS(STB, do_ldst_D, false, true, MO_UB)
> +TRANS(STBX, do_ldst_X, false, true, MO_UB)
> +TRANS(STBU, do_ldst_D, true, true, MO_UB)
> +TRANS(STBUX, do_ldst_X, true, true, MO_UB)
> +
> +/* Store Halfword */
> +TRANS(STH, do_ldst_D, false, true, MO_UW)
> +TRANS(STHX, do_ldst_X, false, true, MO_UW)
> +TRANS(STHU, do_ldst_D, true, true, MO_UW)
> +TRANS(STHUX, do_ldst_X, true, true, MO_UW)
> +
> +/* Store Word */
> +TRANS(STW, do_ldst_D, false, true, MO_UL)
> +TRANS(STWX, do_ldst_X, false, true, MO_UL)
> +TRANS(STWU, do_ldst_D, true, true, MO_UL)
> +TRANS(STWUX, do_ldst_X, true, true, MO_UL)
> +
> +/* Store Doubleword */
> +TRANS64(STD, do_ldst_D, false, true, MO_Q)
> +TRANS64(STDX, do_ldst_X, false, true, MO_Q)
> +TRANS64(STDU, do_ldst_D, true, true, MO_Q)
> +TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
> +
> /*
> * Fixed-Point Arithmetic Instructions
> */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-05-18 1:49 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 20:50 [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-18 0:13 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-18 0:14 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-18 0:15 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-18 0:17 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-18 0:21 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-18 0:23 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-18 0:25 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-18 0:35 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
2021-05-18 0:36 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
2021-05-18 0:37 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-18 0:44 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-18 0:45 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-18 0:47 ` David Gibson [this message]
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-18 0:49 ` David Gibson
2021-05-18 9:48 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-18 0:51 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-18 0:52 ` David Gibson
2021-05-18 9:54 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-18 0:53 ` David Gibson
2021-05-18 9:55 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18 0:56 ` David Gibson
2021-05-18 10:12 ` Richard Henderson
2021-05-21 17:25 ` Matheus K. Ferst
2021-05-24 18:51 ` Richard Henderson
2021-05-26 15:17 ` Matheus K. Ferst
2021-05-26 16:11 ` Richard Henderson
2021-05-27 1:11 ` David Gibson
2021-05-18 3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson
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