* [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
` (13 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These will be used by the decodetree trans_* functions
to early-exit when the instruction set is not enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e16a2721e2..11fd3342a0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7664,6 +7664,32 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for trans_* functions to check for specific insns flags.
+ * Use token pasting to ensure that we use the proper flag with the
+ * proper variable.
+ */
+#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+/* Then special-case the check for 64-bit so that we elide code for ppc32. */
+#if TARGET_LONG_BITS == 32
+# define REQUIRE_64BIT(CTX) return false
+#else
+# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
+#endif
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns matheus.ferst
` (12 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
With prefixed instructions, the number of instructions
remaining until the page crossing is no longer constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 11fd3342a0..d2c9fd9dd7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -8821,9 +8821,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
ctx->base.max_insns = 1;
- } else {
- int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
}
@@ -8874,6 +8871,12 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
gen_invalid(ctx);
}
+ /* End the TB when crossing a page boundary. */
+ if (ctx->base.is_jmp == DISAS_NEXT &&
+ !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+
translator_loop_temp_check(&ctx->base);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
` (11 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/cpu.h | 1 +
target/ppc/insn32.decode | 18 +++++++++++
target/ppc/insn64.decode | 18 +++++++++++
target/ppc/meson.build | 9 ++++++
target/ppc/translate.c | 37 ++++++++++++++++++----
target/ppc/translate/fixedpoint-impl.c.inc | 18 +++++++++++
6 files changed, 95 insertions(+), 6 deletions(-)
create mode 100644 target/ppc/insn32.decode
create mode 100644 target/ppc/insn64.decode
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b0934d9be4..ad34c479ec 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -144,6 +144,7 @@ enum {
POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
+ POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
/* Exception subtypes for POWERPC_EXCP_PROGRAM */
/* FP exceptions */
POWERPC_EXCP_FP = 0x10,
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
new file mode 100644
index 0000000000..a3a8ae06bf
--- /dev/null
+++ b/target/ppc/insn32.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 32-bit insns (opcode space 0)
+#
+# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
new file mode 100644
index 0000000000..a38b1f84dc
--- /dev/null
+++ b/target/ppc/insn64.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
+#
+# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index a6a53a8d5c..a4f18ff414 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -20,6 +20,15 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files(
ppc_ss.add(libdecnumber)
+gen = [
+ decodetree.process('insn32.decode',
+ extra_args: '--static-decode=decode_insn32'),
+ decodetree.process('insn64.decode',
+ extra_args: ['--static-decode=decode_insn64',
+ '--insnwidth=64']),
+]
+ppc_ss.add(gen)
+
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d2c9fd9dd7..f3f464c654 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7690,6 +7690,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+#include "decode-insn32.c.inc"
+#include "decode-insn64.c.inc"
+#include "translate/fixedpoint-impl.c.inc"
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
@@ -8850,11 +8854,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
return true;
}
+static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ return opc1(insn) == 1;
+}
+
static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = cs->env_ptr;
+ target_ulong pc;
uint32_t insn;
bool ok;
@@ -8862,18 +8873,32 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
- ctx->cia = ctx->base.pc_next;
- insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
- ctx->base.pc_next += 4;
+ ctx->cia = pc = ctx->base.pc_next;
+ insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
+ ctx->base.pc_next = pc += 4;
- ok = decode_legacy(cpu, ctx, insn);
+ if (!is_prefix_insn(ctx, insn)) {
+ ok = (decode_insn32(ctx, insn) ||
+ decode_legacy(cpu, ctx, insn));
+ } else if ((pc & 63) == 0) {
+ /*
+ * Power v3.1, section 1.9 Exceptions:
+ * attempt to execute a prefixed instruction that crosses a
+ * 64-byte address boundary (system alignment error).
+ */
+ gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
+ ok = true;
+ } else {
+ uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
+ ctx->base.pc_next = pc += 4;
+ ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
+ }
if (!ok) {
gen_invalid(ctx);
}
/* End the TB when crossing a page boundary. */
- if (ctx->base.is_jmp == DISAS_NEXT &&
- !(ctx->base.pc_next & ~TARGET_PAGE_MASK)) {
+ if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
new file mode 100644
index 0000000000..be75085cee
--- /dev/null
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -0,0 +1,18 @@
+/*
+ * Power ISA decode for Fixed-Point Facility instructions
+ *
+ * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (2 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 05/14] target/ppc: Implement PNOP matheus.ferst
` (10 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 8 ++++
target/ppc/insn64.decode | 12 ++++++
target/ppc/translate.c | 29 --------------
target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++
4 files changed, 64 insertions(+), 29 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a3a8ae06bf..e7c062d8b4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -16,3 +16,11 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+&D rt ra si:int64_t
+@D ...... rt:5 ra:5 si:s16 &D
+
+### Fixed-Point Arithmetic Instructions
+
+ADDI 001110 ..... ..... ................ @D
+ADDIS 001111 ..... ..... ................ @D
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index a38b1f84dc..1965088915 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -16,3 +16,15 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+# Format MLS:D and 8LS:D
+&PLS_D rt ra si:int64_t r:bool
+%pls_si 32:s18 0:16
+@PLS_D ...... .. ... r:1 .. .................. \
+ ...... rt:5 ra:5 ................ \
+ &PLS_D si=%pls_si
+
+### Fixed-Point Arithmetic Instructions
+
+PADDI 000001 10 0--.-- .................. \
+ 001110 ..... ..... ................ @PLS_D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f3f464c654..3012c7447a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1760,19 +1760,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
/* addze addze. addzeo addzeo.*/
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addi */
-static void gen_addi(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* li case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm);
- }
-}
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
@@ -1792,20 +1779,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addis */
-static void gen_addis(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* lis case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm << 16);
- }
-}
-
/* addpcis */
static void gen_addpcis(DisasContext *ctx)
{
@@ -7817,10 +7790,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index be75085cee..344a3ed54b 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -16,3 +16,47 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+/*
+ * Incorporate CIA into the constant when R=1.
+ * Validate that when R=1, RA=0.
+ */
+static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
+{
+ d->rt = a->rt;
+ d->ra = a->ra;
+ d->si = a->si;
+ if (a->r) {
+ if (unlikely(a->ra != 0)) {
+ gen_invalid(ctx);
+ return false;
+ }
+ d->si += ctx->cia;
+ }
+ return true;
+}
+
+static bool trans_ADDI(DisasContext *ctx, arg_D *a)
+{
+ if (a->ra) {
+ tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
+ } else {
+ tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
+ }
+ return true;
+}
+
+static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return trans_ADDI(ctx, &d);
+}
+
+static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
+{
+ a->si <<= 16;
+ return trans_ADDI(ctx, a);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 05/14] target/ppc: Implement PNOP
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (3 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
` (9 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The illegal suffix behavior matches what was observed in a
POWER10 DD2.0 machine.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 67 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 11 ++++
2 files changed, 78 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 1965088915..9aa5097a98 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -28,3 +28,70 @@
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
+
+### Prefixed No-operation Instruction
+
+@PNOP 000001 11 0000-- 000000000000000000 \
+ ................................
+
+{
+ [
+ ## Invalid suffixes: Branch instruction
+ # bc[l][a]
+ INVALID ................................ \
+ 010000-------------------------- @PNOP
+ # b[l][a]
+ INVALID ................................ \
+ 010010-------------------------- @PNOP
+ # bclr[l]
+ INVALID ................................ \
+ 010011---------------0000010000- @PNOP
+ # bcctr[l]
+ INVALID ................................ \
+ 010011---------------1000010000- @PNOP
+ # bctar[l]
+ INVALID ................................ \
+ 010011---------------1000110000- @PNOP
+
+ ## Invalid suffixes: rfebb
+ INVALID ................................ \
+ 010011---------------0010010010- @PNOP
+
+ ## Invalid suffixes: context synchronizing other than isync
+ # sc
+ INVALID ................................ \
+ 010001------------------------1- @PNOP
+ # scv
+ INVALID ................................ \
+ 010001------------------------01 @PNOP
+ # rfscv
+ INVALID ................................ \
+ 010011---------------0001010010- @PNOP
+ # rfid
+ INVALID ................................ \
+ 010011---------------0000010010- @PNOP
+ # hrfid
+ INVALID ................................ \
+ 010011---------------0100010010- @PNOP
+ # urfid
+ INVALID ................................ \
+ 010011---------------0100110010- @PNOP
+ # stop
+ INVALID ................................ \
+ 010011---------------0101110010- @PNOP
+ # mtmsr w/ L=0
+ INVALID ................................ \
+ 011111---------0-----0010010010- @PNOP
+ # mtmsrd w/ L=0
+ INVALID ................................ \
+ 011111---------0-----0010110010- @PNOP
+
+ ## Invalid suffixes: Service Processor Attention
+ INVALID ................................ \
+ 000000----------------100000000- @PNOP
+ ]
+
+ ## Valid suffixes
+ PNOP ................................ \
+ -------------------------------- @PNOP
+}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 344a3ed54b..ce034a14a7 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -60,3 +60,14 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
a->si <<= 16;
return trans_ADDI(ctx, a);
}
+
+static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
+{
+ gen_invalid(ctx);
+ return true;
+}
+
+static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
+{
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (4 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 05/14] target/ppc: Implement PNOP matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions matheus.ferst
` (8 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 37 ++++++
target/ppc/translate.c | 147 ++++-----------------
target/ppc/translate/fixedpoint-impl.c.inc | 89 +++++++++++++
3 files changed, 150 insertions(+), 123 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e7c062d8b4..70f64c235b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,43 @@
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
+%ds_si 2:s14 !function=times_4
+@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+
+&X rt ra rb
+@X ...... rt:5 ra:5 rb:5 .......... . &X
+
+### Fixed-Point Load Instructions
+
+LBZ 100010 ..... ..... ................ @D
+LBZU 100011 ..... ..... ................ @D
+LBZX 011111 ..... ..... ..... 0001010111 - @X
+LBZUX 011111 ..... ..... ..... 0001110111 - @X
+
+LHZ 101000 ..... ..... ................ @D
+LHZU 101001 ..... ..... ................ @D
+LHZX 011111 ..... ..... ..... 0100010111 - @X
+LHZUX 011111 ..... ..... ..... 0100110111 - @X
+
+LHA 101010 ..... ..... ................ @D
+LHAU 101011 ..... ..... ................ @D
+LHAX 011111 ..... ..... ..... 0101010111 - @X
+LHAXU 011111 ..... ..... ..... 0101110111 - @X
+
+LWZ 100000 ..... ..... ................ @D
+LWZU 100001 ..... ..... ................ @D
+LWZX 011111 ..... ..... ..... 0000010111 - @X
+LWZUX 011111 ..... ..... ..... 0000110111 - @X
+
+LWA 111010 ..... ..... ..............10 @DS
+LWAX 011111 ..... ..... ..... 0101010101 - @X
+LWAUX 011111 ..... ..... ..... 0101110101 - @X
+
+LD 111010 ..... ..... ..............00 @DS
+LDU 111010 ..... ..... ..............01 @DS
+LDX 011111 ..... ..... ..... 0000010101 - @X
+LDUX 011111 ..... ..... ..... 0000110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3012c7447a..d9238d1d10 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3323,54 +3323,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
#endif
-#define GEN_LD(name, ldop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_LDU(name, ldop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0 || \
- rA(ctx->opcode) == rD(ctx->opcode))) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_LDUX(name, ldop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0 || \
- rA(ctx->opcode) == rD(ctx->opcode))) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3389,21 +3341,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_LDS(name, ldop, op, type) \
-GEN_LD(name, ldop, op | 0x20, type); \
-GEN_LDU(name, ldop, op | 0x21, type); \
-GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
-GEN_LDX(name, ldop, 0x17, op | 0x00, type)
-
-/* lbz lbzu lbzux lbzx */
-GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
-/* lha lhau lhaux lhax */
-GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
-/* lhz lhzu lhzux lhzx */
-GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
-/* lwz lwzu lwzux lwzx */
-GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
-
#define GEN_LDEPX(name, ldop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3424,47 +3361,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
#if defined(TARGET_PPC64)
-/* lwaux */
-GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
-/* lwax */
-GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
-/* ldux */
-GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
-/* ldx */
-GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
-
/* CI load/store variants */
GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
-static void gen_ld(DisasContext *ctx)
-{
- TCGv EA;
- if (Rc(ctx->opcode)) {
- if (unlikely(rA(ctx->opcode) == 0 ||
- rA(ctx->opcode) == rD(ctx->opcode))) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
- if (ctx->opcode & 0x02) {
- /* lwa (lwau is undefined) */
- gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
- } else {
- /* ld - ldu */
- gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
- }
- if (Rc(ctx->opcode)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
- }
- tcg_temp_free(EA);
-}
-
/* lq */
static void gen_lq(DisasContext *ctx)
{
@@ -7637,6 +7539,14 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for decodetree used by !function for decoding arguments.
+ */
+static int times_4(DisasContext *ctx, int x)
+{
+ return x * 4;
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
@@ -7663,6 +7573,21 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+/*
+ * Helpers for implementing sets of trans_* functions.
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
+ */
+#define TRANS(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { return FUNC(ctx, a, __VA_ARGS__); }
+
+#define TRANS64(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
+
+/* TODO: More TRANS* helpers for extra insn_flags checks. */
+
+
#include "decode-insn32.c.inc"
#include "decode-insn64.c.inc"
#include "translate/fixedpoint-impl.c.inc"
@@ -7847,7 +7772,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
PPC_NONE, PPC2_ISA300),
#endif
#if defined(TARGET_PPC64)
-GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
@@ -8213,34 +8137,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09),
GEN_PPC64_R4(rldimi, 0x1E, 0x06),
#endif
-#undef GEN_LD
-#undef GEN_LDU
-#undef GEN_LDUX
#undef GEN_LDX_E
-#undef GEN_LDS
-#define GEN_LD(name, ldop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDU(name, ldop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUX(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
-#define GEN_LDS(name, ldop, op, type) \
-GEN_LD(name, ldop, op | 0x20, type) \
-GEN_LDU(name, ldop, op | 0x21, type) \
-GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
-GEN_LDX(name, ldop, 0x17, op | 0x00, type)
-
-GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
-GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
-GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
-GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
-GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
-GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
-GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
/* HV/P7 and later only */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index ce034a14a7..6140dd41ca 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -36,6 +36,95 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
return true;
}
+/*
+ * Fixed-Point Load/Store Instructions
+ */
+
+static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
+ bool store, MemOp mop)
+{
+ TCGv ea;
+
+ if (update && (ra == 0 || (!store && ra == rt))) {
+ gen_invalid(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+
+ ea = tcg_temp_new();
+ if (ra) {
+ tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
+ } else {
+ tcg_gen_mov_tl(ea, displ);
+ }
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(ea, ea);
+ }
+ mop ^= ctx->default_tcg_memop_mask;
+ if (store) {
+ tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ }
+ if (update) {
+ tcg_gen_mov_tl(cpu_gpr[ra], ea);
+ }
+ tcg_temp_free(ea);
+
+ return true;
+}
+
+static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
+ MemOp mop)
+{
+ return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
+}
+
+static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
+ bool store, MemOp mop)
+{
+ return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
+}
+
+/* Load Byte and Zero */
+TRANS(LBZ, do_ldst_D, false, false, MO_UB)
+TRANS(LBZX, do_ldst_X, false, false, MO_UB)
+TRANS(LBZU, do_ldst_D, true, false, MO_UB)
+TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+
+/* Load Halfword and Zero */
+TRANS(LHZ, do_ldst_D, false, false, MO_UW)
+TRANS(LHZX, do_ldst_X, false, false, MO_UW)
+TRANS(LHZU, do_ldst_D, true, false, MO_UW)
+TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+
+/* Load Halfword Algebraic */
+TRANS(LHA, do_ldst_D, false, false, MO_SW)
+TRANS(LHAX, do_ldst_X, false, false, MO_SW)
+TRANS(LHAU, do_ldst_D, true, false, MO_SW)
+TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+
+/* Load Word and Zero */
+TRANS(LWZ, do_ldst_D, false, false, MO_UL)
+TRANS(LWZX, do_ldst_X, false, false, MO_UL)
+TRANS(LWZU, do_ldst_D, true, false, MO_UL)
+TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+
+/* Load Word Algebraic */
+TRANS64(LWA, do_ldst_D, false, false, MO_SL)
+TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
+TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+
+/* Load Doubleword */
+TRANS64(LD, do_ldst_D, false, false, MO_Q)
+TRANS64(LDX, do_ldst_X, false, false, MO_Q)
+TRANS64(LDU, do_ldst_D, true, false, MO_Q)
+TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+
+/*
+ * Fixed-Point Arithmetic Instructions
+ */
+
static bool trans_ADDI(DisasContext *ctx, arg_D *a)
{
if (a->ra) {
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (5 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
` (7 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 15 +++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 9aa5097a98..547bd1736f 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -24,6 +24,21 @@
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+### Fixed-Point Load Instructions
+
+PLBZ 000001 10 0--.-- .................. \
+ 100010 ..... ..... ................ @PLS_D
+PLHZ 000001 10 0--.-- .................. \
+ 101000 ..... ..... ................ @PLS_D
+PLHA 000001 10 0--.-- .................. \
+ 101010 ..... ..... ................ @PLS_D
+PLWZ 000001 10 0--.-- .................. \
+ 100000 ..... ..... ................ @PLS_D
+PLWA 000001 00 0--.-- .................. \
+ 101001 ..... ..... ................ @PLS_D
+PLD 000001 00 0--.-- .................. \
+ 111001 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 6140dd41ca..7687f31d6f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
}
+static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
+ bool store, MemOp mop)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return do_ldst_D(ctx, &d, update, store, mop);
+}
+
static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
bool store, MemOp mop)
{
@@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
TRANS(LBZU, do_ldst_D, true, false, MO_UB)
TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB)
/* Load Halfword and Zero */
TRANS(LHZ, do_ldst_D, false, false, MO_UW)
TRANS(LHZX, do_ldst_X, false, false, MO_UW)
TRANS(LHZU, do_ldst_D, true, false, MO_UW)
TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW)
/* Load Halfword Algebraic */
TRANS(LHA, do_ldst_D, false, false, MO_SW)
TRANS(LHAX, do_ldst_X, false, false, MO_SW)
TRANS(LHAU, do_ldst_D, true, false, MO_SW)
TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW)
/* Load Word and Zero */
TRANS(LWZ, do_ldst_D, false, false, MO_UL)
TRANS(LWZX, do_ldst_X, false, false, MO_UL)
TRANS(LWZU, do_ldst_D, true, false, MO_UL)
TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL)
/* Load Word Algebraic */
TRANS64(LWA, do_ldst_D, false, false, MO_SL)
TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL)
/* Load Doubleword */
TRANS64(LD, do_ldst_D, false, false, MO_Q)
TRANS64(LDX, do_ldst_X, false, false, MO_Q)
TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (6 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions matheus.ferst
` (6 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 22 ++++++
target/ppc/translate.c | 85 +---------------------
target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++
3 files changed, 49 insertions(+), 82 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 70f64c235b..00ec0f4328 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
+### Fixed-Point Store Instructions
+
+STB 100110 ..... ..... ................ @D
+STBU 100111 ..... ..... ................ @D
+STBX 011111 ..... ..... ..... 0011010111 - @X
+STBUX 011111 ..... ..... ..... 0011110111 - @X
+
+STH 101100 ..... ..... ................ @D
+STHU 101101 ..... ..... ................ @D
+STHX 011111 ..... ..... ..... 0110010111 - @X
+STHUX 011111 ..... ..... ..... 0110110111 - @X
+
+STW 100100 ..... ..... ................ @D
+STWU 100101 ..... ..... ................ @D
+STWX 011111 ..... ..... ..... 0010010111 - @X
+STWUX 011111 ..... ..... ..... 0010110111 - @X
+
+STD 111110 ..... ..... ..............00 @DS
+STDU 111110 ..... ..... ..............01 @DS
+STDX 011111 ..... ..... ..... 0010010101 - @X
+STDUX 011111 ..... ..... ..... 0010110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d9238d1d10..3c3cb1b664 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3299,7 +3299,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
}
+#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
+#endif
GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
@@ -3432,52 +3434,6 @@ static void gen_lq(DisasContext *ctx)
#endif
/*** Integer store ***/
-#define GEN_ST(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STU(name, stop, opc, type) \
-static void glue(gen_, stop##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3495,19 +3451,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type); \
-GEN_STU(name, stop, op | 0x21, type); \
-GEN_STUX(name, stop, 0x17, op | 0x01, type); \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-/* stb stbu stbux stbx */
-GEN_STS(stb, st8, 0x06, PPC_INTEGER);
-/* sth sthu sthux sthx */
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
-/* stw stwu stwux stwx */
-GEN_STS(stw, st32, 0x04, PPC_INTEGER);
-
#define GEN_STEPX(name, stop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3529,8 +3472,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
#endif
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
@@ -8166,31 +8107,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
-#undef GEN_ST
-#undef GEN_STU
-#undef GEN_STUX
#undef GEN_STX_E
-#undef GEN_STS
-#define GEN_ST(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STU(name, stop, opc, type) \
-GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type) \
-GEN_STU(name, stop, op | 0x21, type) \
-GEN_STUX(name, stop, 0x17, op | 0x01, type) \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-GEN_STS(stb, st8, 0x06, PPC_INTEGER)
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
-GEN_STS(stw, st32, 0x04, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 7687f31d6f..adeee33289 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
+/* Store Byte */
+TRANS(STB, do_ldst_D, false, true, MO_UB)
+TRANS(STBX, do_ldst_X, false, true, MO_UB)
+TRANS(STBU, do_ldst_D, true, true, MO_UB)
+TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+
+/* Store Halfword */
+TRANS(STH, do_ldst_D, false, true, MO_UW)
+TRANS(STHX, do_ldst_X, false, true, MO_UW)
+TRANS(STHU, do_ldst_D, true, true, MO_UW)
+TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+
+/* Store Word */
+TRANS(STW, do_ldst_D, false, true, MO_UL)
+TRANS(STWX, do_ldst_X, false, true, MO_UL)
+TRANS(STWU, do_ldst_D, true, true, MO_UL)
+TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+
+/* Store Doubleword */
+TRANS64(STD, do_ldst_D, false, true, MO_Q)
+TRANS64(STDX, do_ldst_X, false, true, MO_Q)
+TRANS64(STDU, do_ldst_D, true, true, MO_Q)
+TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+
/*
* Fixed-Point Arithmetic Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (7 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
` (5 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 12 ++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 547bd1736f..72c5944a53 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+### Fixed-Point Store Instructions
+
+PSTW 000001 10 0--.-- .................. \
+ 100100 ..... ..... ................ @PLS_D
+PSTB 000001 10 0--.-- .................. \
+ 100110 ..... ..... ................ @PLS_D
+PSTH 000001 10 0--.-- .................. \
+ 101100 ..... ..... ................ @PLS_D
+
+PSTD 000001 00 0--.-- .................. \
+ 111101 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index adeee33289..2d2d874146 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB)
TRANS(STBX, do_ldst_X, false, true, MO_UB)
TRANS(STBU, do_ldst_D, true, true, MO_UB)
TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB)
/* Store Halfword */
TRANS(STH, do_ldst_D, false, true, MO_UW)
TRANS(STHX, do_ldst_X, false, true, MO_UW)
TRANS(STHU, do_ldst_D, true, true, MO_UW)
TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW)
/* Store Word */
TRANS(STW, do_ldst_D, false, true, MO_UL)
TRANS(STWX, do_ldst_X, false, true, MO_UL)
TRANS(STWU, do_ldst_D, true, true, MO_UL)
TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL)
/* Store Doubleword */
TRANS64(STD, do_ldst_D, false, true, MO_Q)
TRANS64(STDX, do_ldst_X, false, true, MO_Q)
TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (8 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 11/14] target/ppc: Implement cfuged instruction matheus.ferst
` (4 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
setbc: Set Boolean Condition
setbcr: Set Boolean Condition Reverse
setnbc: Set Negative Boolean Condition
setnbcr: Set Negative Boolean Condition Reverse
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 10 ++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 23 ++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 00ec0f4328..bc69c70493 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -26,6 +26,9 @@
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
+&X_bi rt bi
+@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+
+### Move To/From System Register Instructions
+
+SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
+SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
+SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
+SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 2d2d874146..5f9845fa40 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -204,3 +204,26 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
{
return true;
}
+
+static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ uint32_t mask = 0x08 >> (a->bi & 0x03);
+ TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE;
+ TCGv temp = tcg_temp_new();
+
+ tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
+ tcg_gen_andi_tl(temp, temp, mask);
+ tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0);
+ if (neg) {
+ tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]);
+ }
+ tcg_temp_free(temp);
+
+ return true;
+}
+
+TRANS(SETBC, do_set_bool_cond, false, false)
+TRANS(SETBCR, do_set_bool_cond, false, true)
+TRANS(SETNBC, do_set_bool_cond, true, false)
+TRANS(SETNBCR, do_set_bool_cond, true, true)
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 11/14] target/ppc: Implement cfuged instruction
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (9 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 21:02 ` Richard Henderson
2021-06-01 19:35 ` [PATCH v6 12/14] target/ppc: Implement vcfuged instruction matheus.ferst
` (3 subsequent siblings)
14 siblings, 1 reply; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 ++
target/ppc/int_helper.c | 62 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++
4 files changed, 79 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea9f2a236c..c517b9f025 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
+DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index bc69c70493..d4044d9069 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+## Fixed-Point Logical Instructions
+
+CFUGED 011111 ..... ..... ..... 0011011100 - @X
+
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 41f8477d4b..efa833ef64 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
+uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+{
+ /*
+ * Instead of processing the mask bit-by-bit from the most significant to
+ * the least significant bit, as described in PowerISA, we'll handle it in
+ * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to use
+ * ctz or cto, we negate the mask at the end of the loop.
+ */
+ target_ulong m, left = 0, right = 0;
+ unsigned int n, i = 64;
+ bool bit = false; /* tracks if we are processing zeros or ones */
+
+ if (mask == 0 || mask == -1) {
+ return src;
+ }
+
+ /* Processes the mask in blocks, from LSB to MSB */
+ while (i) {
+ /* Find how many bits we should take */
+ n = ctz64(mask);
+ if (n > i) {
+ n = i;
+ }
+
+ /*
+ * Extracts 'n' trailing bits of src and put them on the leading 'n'
+ * bits of 'right' or 'left', pushing down the previously extracted
+ * values.
+ */
+ m = (1ll << n) - 1;
+ if (bit) {
+ right = ror64(right | (src & m), n);
+ } else {
+ left = ror64(left | (src & m), n);
+ }
+
+ /*
+ * Discards the processed bits from 'src' and 'mask'. Note that we are
+ * removing 'n' trailing zeros from 'mask', but the logical shift will
+ * add 'n' leading zeros back, so the population count of 'mask' is kept
+ * the same.
+ */
+ src >>= n;
+ mask >>= n;
+ i -= n;
+ bit = !bit;
+ mask = ~mask;
+ }
+
+ /*
+ * At the end, right was ror'ed ctpop(mask) times. To put it back in place,
+ * we'll shift it more 64-ctpop(mask) times.
+ */
+ if (bit) {
+ n = ctpop64(mask);
+ } else {
+ n = 64 - ctpop64(mask);
+ }
+
+ return left | (right >> n);
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 5f9845fa40..50933a3b9d 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false)
TRANS(SETBCR, do_set_bool_cond, false, true)
TRANS(SETNBC, do_set_bool_cond, true, false)
TRANS(SETNBCR, do_set_bool_cond, true, true)
+
+static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 11/14] target/ppc: Implement cfuged instruction
2021-06-01 19:35 ` [PATCH v6 11/14] target/ppc: Implement cfuged instruction matheus.ferst
@ 2021-06-01 21:02 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2021-06-01 21:02 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: groug, f4bug, luis.pires, lagarcia, david
On 6/1/21 12:35 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> target/ppc/helper.h | 1 +
> target/ppc/insn32.decode | 4 ++
> target/ppc/int_helper.c | 62 ++++++++++++++++++++++
> target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++
> 4 files changed, 79 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 12/14] target/ppc: Implement vcfuged instruction
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (10 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 11/14] target/ppc: Implement cfuged instruction matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 21:09 ` Richard Henderson
2021-06-01 19:35 ` [PATCH v6 13/14] target/ppc: Move addpcis to decodetree matheus.ferst
` (2 subsequent siblings)
14 siblings, 1 reply; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 7 ++++
target/ppc/translate.c | 1 +
target/ppc/translate/vector-impl.c.inc | 56 ++++++++++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 target/ppc/translate/vector-impl.c.inc
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d4044d9069..77edf407ab 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,9 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&VX vrt vra vrb
+@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+
+## Vector Bit Manipulation Instruction
+
+VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3c3cb1b664..ed5515f8e2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7538,6 +7538,7 @@ static int times_4(DisasContext *ctx, int x)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
+#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
new file mode 100644
index 0000000000..117ce9b137
--- /dev/null
+++ b/target/ppc/translate/vector-impl.c.inc
@@ -0,0 +1,56 @@
+/*
+ * Power ISA decode for Vector Facility instructions
+ *
+ * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ALTIVEC(CTX) \
+ do { \
+ if (unlikely(!(CTX)->altivec_enabled)) { \
+ gen_exception((CTX), POWERPC_EXCP_VPU); \
+ return true; \
+ } \
+ } while (0)
+
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 tgt, src, mask;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_ALTIVEC(ctx);
+
+ tgt = tcg_temp_new_i64();
+ src = tcg_temp_new_i64();
+ mask = tcg_temp_new_i64();
+
+ /* centrifuge lower double word */
+ get_cpu_vsrl(src, a->vra + 32);
+ get_cpu_vsrl(mask, a->vrb + 32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrl(a->vrt + 32, tgt);
+
+ /* centrifuge higher double word */
+ get_cpu_vsrh(src, a->vra + 32);
+ get_cpu_vsrh(mask, a->vrb + 32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrh(a->vrt + 32, tgt);
+
+ tcg_temp_free_i64(tgt);
+ tcg_temp_free_i64(src);
+ tcg_temp_free_i64(mask);
+
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 12/14] target/ppc: Implement vcfuged instruction
2021-06-01 19:35 ` [PATCH v6 12/14] target/ppc: Implement vcfuged instruction matheus.ferst
@ 2021-06-01 21:09 ` Richard Henderson
2021-06-02 8:51 ` David Gibson
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2021-06-01 21:09 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: groug, f4bug, luis.pires, lagarcia, david
On 6/1/21 12:35 PM, matheus.ferst@eldorado.org.br wrote:
> +++ b/target/ppc/translate/vector-impl.c.inc
> @@ -0,0 +1,56 @@
> +/*
> + * Power ISA decode for Vector Facility instructions
> + *
> + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ALTIVEC(CTX) \
> + do { \
> + if (unlikely(!(CTX)->altivec_enabled)) { \
> + gen_exception((CTX), POWERPC_EXCP_VPU); \
> + return true; \
> + } \
> + } while (0)
I think it would be better to name this REQUIRE_VECTOR, to match the
Vector_Unavailable() pseudo-code in the current manual.
Also, I think you should place this in translate.c, because you will also need
this for VSX.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v6 12/14] target/ppc: Implement vcfuged instruction
2021-06-01 21:09 ` Richard Henderson
@ 2021-06-02 8:51 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2021-06-02 8:51 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, f4bug, luis.pires, qemu-ppc, lagarcia, matheus.ferst,
groug
[-- Attachment #1: Type: text/plain, Size: 2090 bytes --]
On Tue, Jun 01, 2021 at 02:09:22PM -0700, Richard Henderson wrote:
> On 6/1/21 12:35 PM, matheus.ferst@eldorado.org.br wrote:
> > +++ b/target/ppc/translate/vector-impl.c.inc
> > @@ -0,0 +1,56 @@
> > +/*
> > + * Power ISA decode for Vector Facility instructions
> > + *
> > + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#define REQUIRE_ALTIVEC(CTX) \
> > + do { \
> > + if (unlikely(!(CTX)->altivec_enabled)) { \
> > + gen_exception((CTX), POWERPC_EXCP_VPU); \
> > + return true; \
> > + } \
> > + } while (0)
>
> I think it would be better to name this REQUIRE_VECTOR, to match the
> Vector_Unavailable() pseudo-code in the current manual.
>
> Also, I think you should place this in translate.c, because you will also
> need this for VSX.
I think those can reasonably be followup changes.
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 13/14] target/ppc: Move addpcis to decodetree
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (11 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 12/14] target/ppc: Implement vcfuged instruction matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 19:35 ` [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-06-02 8:53 ` [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions David Gibson
14 siblings, 0 replies; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 6 ++++++
target/ppc/translate.c | 9 ---------
target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 77edf407ab..93e5d44d9e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,10 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&DX rt d
+%dx_d 6:s10 16:5 0:1
+@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@@ -90,6 +94,8 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+ADDPCIS 010011 ..... ..... .......... 00010 . @DX
+
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ed5515f8e2..35d8831d44 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1779,14 +1779,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addpcis */
-static void gen_addpcis(DisasContext *ctx)
-{
- target_long d = DX(ctx->opcode);
-
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
-}
-
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
{
@@ -7659,7 +7651,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 50933a3b9d..2713366791 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
return trans_ADDI(ctx, a);
}
+static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d << 16));
+ return true;
+}
+
static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
{
gen_invalid(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (12 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 13/14] target/ppc: Move addpcis to decodetree matheus.ferst
@ 2021-06-01 19:35 ` matheus.ferst
2021-06-01 20:57 ` Richard Henderson
2021-06-02 8:53 ` [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions David Gibson
14 siblings, 1 reply; 21+ messages in thread
From: matheus.ferst @ 2021-06-01 19:35 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, groug, luis.pires, lagarcia,
Matheus Ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The
Programming Environments Manual:
"For 32-bit implementations, the L field must be cleared, otherwise the
instruction form is invalid."
Some CPUs are known to deviate from this specification by ignoring the
L bit [1]. The stricter behavior, however, can help users that test
software with qemu, making it more likely to detect bugs that would
otherwise be silent.
If deemed necessary, a future patch can adapt this behavior based on
the specific CPU model.
[1] The 601 manual is the only one I've found that explicitly states
that the L bit is ignored, but we also observe this behavior in a 7447A
v1.2.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 14 ++++++
target/ppc/translate.c | 52 ----------------------
target/ppc/translate/fixedpoint-impl.c.inc | 33 +++++++++++++-
3 files changed, 46 insertions(+), 53 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 93e5d44d9e..9fd8d6b817 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,10 @@
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
+&D_bf bf l:bool ra imm
+@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
+@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -36,6 +40,9 @@
&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+&X_bfl bf l:bool ra rb
+@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -89,6 +96,13 @@ STDU 111110 ..... ..... ..............01 @DS
STDX 011111 ..... ..... ..... 0010010101 - @X
STDUX 011111 ..... ..... ..... 0010110101 - @X
+### Fixed-Point Compare Instructions
+
+CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
+CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
+CMPI 001011 ... - . ..... ................ @D_bfs
+CMPLI 001010 ... - . ..... ................ @D_bfu
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 35d8831d44..95e4d9b815 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1489,54 +1489,6 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
}
}
-/* cmp */
-static void gen_cmp(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 1, crfD(ctx->opcode));
- } else {
- gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 1, crfD(ctx->opcode));
- }
-}
-
-/* cmpi */
-static void gen_cmpi(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
- 1, crfD(ctx->opcode));
- } else {
- gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
- 1, crfD(ctx->opcode));
- }
-}
-
-/* cmpl */
-static void gen_cmpl(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 0, crfD(ctx->opcode));
- } else {
- gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 0, crfD(ctx->opcode));
- }
-}
-
-/* cmpli */
-static void gen_cmpli(DisasContext *ctx)
-{
- if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
- gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
- 0, crfD(ctx->opcode));
- } else {
- gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
- 0, crfD(ctx->opcode));
- }
-}
-
/* cmprb - range comparison: isupper, isaplha, islower*/
static void gen_cmprb(DisasContext *ctx)
{
@@ -7639,10 +7591,6 @@ GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
#endif
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
-GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
-GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
-GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
-GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 2713366791..1e0957f5eb 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -1,4 +1,4 @@
-/*
+ /*
* Power ISA decode for Fixed-Point Facility instructions
*
* Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
@@ -165,6 +165,37 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
+/*
+ * Fixed-Point Compare Instructions
+ */
+
+static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s)
+{
+ if (a->l) {
+ REQUIRE_64BIT(ctx);
+ gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
+ } else {
+ gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
+ }
+ return true;
+}
+
+static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s)
+{
+ if (a->l) {
+ REQUIRE_64BIT(ctx);
+ gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
+ } else {
+ gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
+ }
+ return true;
+}
+
+TRANS(CMP, do_cmp_X, true);
+TRANS(CMPL, do_cmp_X, false);
+TRANS(CMPI, do_cmp_D, true);
+TRANS(CMPLI, do_cmp_D, false);
+
/*
* Fixed-Point Arithmetic Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-06-01 19:35 ` [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
@ 2021-06-01 20:57 ` Richard Henderson
2021-06-02 8:53 ` David Gibson
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2021-06-01 20:57 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: groug, f4bug, luis.pires, lagarcia, david
On 6/1/21 12:35 PM, matheus.ferst@eldorado.org.br wrote:
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -1,4 +1,4 @@
> -/*
> + /*
> * Power ISA decode for Fixed-Point Facility instructions
Watch the whitespace errors.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
2021-06-01 20:57 ` Richard Henderson
@ 2021-06-02 8:53 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2021-06-02 8:53 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, f4bug, luis.pires, qemu-ppc, lagarcia, matheus.ferst,
groug
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On Tue, Jun 01, 2021 at 01:57:25PM -0700, Richard Henderson wrote:
> On 6/1/21 12:35 PM, matheus.ferst@eldorado.org.br wrote:
> > --- a/target/ppc/translate/fixedpoint-impl.c.inc
> > +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> > @@ -1,4 +1,4 @@
> > -/*
> > + /*
> > * Power ISA decode for Fixed-Point Facility instructions
>
> Watch the whitespace errors.
I've fixed that up in my tree.
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
` (13 preceding siblings ...)
2021-06-01 19:35 ` [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
@ 2021-06-02 8:53 ` David Gibson
14 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2021-06-02 8:53 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, groug
[-- Attachment #1: Type: text/plain, Size: 3774 bytes --]
On Tue, Jun 01, 2021 at 04:35:14PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> This series provides the basic infrastructure for adding the new 32/64-bit
> instructions in Power ISA 3.1 to target/ppc.
Applied to ppc-for-6.1.
>
> v6:
> - Rebase on ppc-for-6.1;
> - Fix rebase error in patch 02/14;
> - Fix style errors;
> - REQUIRE_64BIT when L=1 in cmp/cmpi/cmpl/cmpli.
>
> v5:
> - Rebase on ppc-for-6.1;
> - Change copyright line from new files;
> - Remove argument set from PNOP;
> - Add comments to explain helper_cfuged implementation;
> - New REQUIRE_ALTIVEC macro;
> - REQUIRE_ALTIVEC and REQUIRE_INSNS_FLAGS2 in trans_CFUGED;
> - cmp/cmpi/cmpl/cmpli moved to decodetree.
>
> v4:
> - Rebase on ppc-for-6.1;
> - Fold do_ldst_D and do_ldst_X;
> - Add tcg_const_tl, used to share do_ldst_D and do_ldst_X code;
> - Unfold prefixed and non-prefixed loads/stores/addi to let non-prefixed insns use the non-prefixed formats;
> - PNOP invalid suffixes;
> - setbc/setbcr/stnbc/setnbcr implemented;
> - cfuged/vcfuged implemented;
> - addpcis moved to decodetree.
>
> v3:
> - More changes for decodetree.
> - Cleanup exception/is_jmp logic to the point exception is removed.
> - Fold in Luis' isa check for prefixed insn support.
> - Share trans_* between prefixed and non-prefixed instructions.
> - Use macros to minimize the trans_* boilerplate.
> - Fix decode mistake for STHX/STHXU.
>
> v2:
> - Store current pc in ctx instead of insn_size
> - Use separate decode files for 32- and 64-bit instructions
> - Improvements to the exception/is_jmp logic
> - Use translator_loop_temp_check()
> - Moved logic to prevent translation from crossing page boundaries
> - Additional instructions using decodetree: addis, pnop, loads/stores
> - Added check for prefixed insn support in cpu flags
>
>
> Matheus Ferst (5):
> target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
> target/ppc: Implement cfuged instruction
> target/ppc: Implement vcfuged instruction
> target/ppc: Move addpcis to decodetree
> target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
>
> Richard Henderson (9):
> target/ppc: Introduce macros to check isa extensions
> target/ppc: Move page crossing check to ppc_tr_translate_insn
> target/ppc: Add infrastructure for prefixed insns
> target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
> target/ppc: Implement PNOP
> target/ppc: Move D/DS/X-form integer loads to decodetree
> target/ppc: Implement prefixed integer load instructions
> target/ppc: Move D/DS/X-form integer stores to decodetree
> target/ppc: Implement prefixed integer store instructions
>
> target/ppc/cpu.h | 1 +
> target/ppc/helper.h | 1 +
> target/ppc/insn32.decode | 126 +++++++
> target/ppc/insn64.decode | 124 +++++++
> target/ppc/int_helper.c | 62 ++++
> target/ppc/meson.build | 9 +
> target/ppc/translate.c | 391 +++++----------------
> target/ppc/translate/fixedpoint-impl.c.inc | 279 +++++++++++++++
> target/ppc/translate/vector-impl.c.inc | 56 +++
> 9 files changed, 747 insertions(+), 302 deletions(-)
> create mode 100644 target/ppc/insn32.decode
> create mode 100644 target/ppc/insn64.decode
> create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
> create mode 100644 target/ppc/translate/vector-impl.c.inc
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 21+ messages in thread