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[82.29.237.198]) by smtp.gmail.com with ESMTPSA id c8sm17755226wri.91.2021.06.29.07.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Jun 2021 07:06:04 -0700 (PDT) Date: Tue, 29 Jun 2021 15:06:02 +0100 From: "Dr. David Alan Gilbert" To: zhenwei pi , babu.moger@amd.com, wei.huang2@amd.com Subject: Re: [PATCH] target/i386: Fix cpuid level for AMD Message-ID: References: <20210628132018.394994-1-pizhenwei@bytedance.com> MIME-Version: 1.0 In-Reply-To: <20210628132018.394994-1-pizhenwei@bytedance.com> User-Agent: Mutt/2.0.7 (2021-05-04) Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.435, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, like.xu@linux.intel.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, armbru@redhat.com, pbonzini@redhat.com, philmd@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" * zhenwei pi (pizhenwei@bytedance.com) wrote: > A AMD server typically has cpuid level 0x10(test on Rome/Milan), it > should not be changed to 0x1f in multi-dies case. > > Fixes: a94e1428991 (target/i386: Add CPUID.1F generation support > for multi-dies PCMachine) > Signed-off-by: zhenwei pi (Copying in Babu) Hmm I think you're right. I've cc'd in Babu and Wei. Eduardo: What do we need to do about compatibility, do we need to wire this to machine type or CPU version? Dave > --- > target/i386/cpu.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index a9fe1662d3..3934c559e4 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -5961,8 +5961,12 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) > } > } > > - /* CPU topology with multi-dies support requires CPUID[0x1F] */ > - if (env->nr_dies > 1) { > + /* > + * Intel CPU topology with multi-dies support requires CPUID[0x1F]. > + * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect > + * extended toplogy by leaf 0xB. Only adjust it for Intel CPU. > + */ > + if ((env->nr_dies > 1) && IS_INTEL_CPU(env)) { > x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); > } > > -- > 2.25.1 > > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK