From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B44EAC432BE for ; Tue, 10 Aug 2021 04:27:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05C0F6101D for ; Tue, 10 Aug 2021 04:27:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 05C0F6101D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:34350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mDJMn-0007D8-Ui for qemu-devel@archiver.kernel.org; Tue, 10 Aug 2021 00:27:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDJDu-0008Fm-LE; Tue, 10 Aug 2021 00:18:42 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:56763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mDJDr-0002RE-9L; Tue, 10 Aug 2021 00:18:42 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4GkKSS1Tfqz9t9y; Tue, 10 Aug 2021 14:18:16 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gibson.dropbear.id.au; s=201602; t=1628569096; bh=bJblPjglavyO4C/eDskg/g4hw/+kMjsz0C+CTgbD7pw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=OlmJnSsxHg/PLo+G5lD85sRLjSRw5yRsfnLUq3s3jHIOyfDfxVGoHUA8D1RLNjsep PXVT81XNJRTZnFpw8nMvxiZmgHX/lo6FtcD1eGC9XuuZkCvxRt6gMuQ1mUUL7T6x6d CwIw3xmvoMUxN330sySKZIO/IYjwPa3fwG0Fo8lg= Date: Tue, 10 Aug 2021 13:50:12 +1000 From: David Gibson To: Daniel Henrique Barboza Subject: Re: [PATCH 09/19] PPC64/TCG: Implement 'rfebb' instruction Message-ID: References: <20210809131057.1694145-1-danielhb413@gmail.com> <20210809131057.1694145-10-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="DoKDLrotvCPMoA3v" Content-Disposition: inline In-Reply-To: <20210809131057.1694145-10-danielhb413@gmail.com> Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Gustavo Romero , qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --DoKDLrotvCPMoA3v Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 09, 2021 at 10:10:47AM -0300, Daniel Henrique Barboza wrote: > From: Gustavo Romero >=20 > An Event-Based Branch (EBB) allows applications to change the NIA when a > event-based exception occurs. Event-based exceptions are enabled by > setting the Branch Event Status and Control Register (BESCR). If the > event-based exception is enabled when the exception occurs, an EBB > happens. >=20 > The EBB will: >=20 > - set the Global Enable (GE) bit of BESCR to 0; > - set bits 0-61 of the Event-Based Branch Return Register (EBBRR) to the > effective address of the NIA that would have executed if the EBB > didn't happen; > - Instruction fetch and execution will continue in the effective address > contained in the Event-Based Branch Handler Register (EBBHR). >=20 > The EBB Handler will process the event and then execute the Return From > Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then > redirects execution to the address pointed in EBBRR. This process is > described in the PowerISA v3.1, Book II, Chapter 6 [1]. >=20 > This patch implements the rfebb instruction. Descriptions of all > relevant BESCR bits are also added - this patch is only using BESCR_GE, > but next patches will use the remaining bits. >=20 > Note that we're implementing the extended rfebb mnemonic (BESCR_GE is > being always set to 1). The basic rfebb instruction would accept an > operand that would be used to set GE. >=20 > [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf >=20 > CC: Gustavo Romero > Signed-off-by: Gustavo Romero > Signed-off-by: Daniel Henrique Barboza > --- > target/ppc/cpu.h | 12 ++++++++++++ > target/ppc/translate.c | 21 +++++++++++++++++++++ > 2 files changed, 33 insertions(+) >=20 > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index afd9cd402b..ae431e65be 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -358,6 +358,18 @@ typedef struct ppc_v3_pate_t { > #define MMCR1_PMC3SEL PPC_BITMASK(48, 55) > #define MMCR1_PMC4SEL PPC_BITMASK(56, 63) > =20 > +/* EBB/BESCR bits */ > +/* Global Enable */ > +#define BESCR_GE PPC_BIT(0) > +/* External Event-based Exception Enable */ > +#define BESCR_EE PPC_BIT(30) > +/* Performance Monitor Event-based Exception Enable */ > +#define BESCR_PME PPC_BIT(31) > +/* External Event-based Exception Occurred */ > +#define BESCR_EEO PPC_BIT(62) > +/* Performance Monitor Event-based Exception Occurred */ > +#define BESCR_PMEO PPC_BIT(63) > + > /* LPCR bits */ > #define LPCR_VPM0 PPC_BIT(0) > #define LPCR_VPM1 PPC_BIT(1) > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 62356cfadf..afc254a03f 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2701,6 +2701,26 @@ static void gen_darn(DisasContext *ctx) > } > } > } > + > +/* rfebb */ > +static void gen_rfebb(DisasContext *ctx) Oof.. not necessarily a nack, but it would be nice to implement any new instructions using the disastree path rather than the old ppc specific decode logic. > +{ > + TCGv target =3D tcg_temp_new(); > + TCGv bescr =3D tcg_temp_new(); > + > + gen_load_spr(target, SPR_EBBRR); > + tcg_gen_mov_tl(cpu_nip, target); > + > + gen_load_spr(bescr, SPR_BESCR); > + tcg_gen_ori_tl(bescr, bescr, BESCR_GE); > + gen_store_spr(SPR_BESCR, bescr); > + > + ctx->base.is_jmp =3D DISAS_EXIT; > + > + tcg_temp_free(target); > + tcg_temp_free(bescr); > +} > + > #endif > =20 > /*** Integer rotate = ***/ > @@ -7724,6 +7744,7 @@ GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, = PPC_POPCNTWD), > GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), > GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA30= 0), > GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), > +GEN_HANDLER_E(rfebb, 0x13, 0x12, 0x04, 0x03FFF001, PPC_NONE, PPC2_ISA207= S), > GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205= ), > GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_= ISA206), > #endif --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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