From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60040C432BE for ; Wed, 25 Aug 2021 05:44:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C6BD61212 for ; Wed, 25 Aug 2021 05:44:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0C6BD61212 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:58332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIliG-0002JF-9k for qemu-devel@archiver.kernel.org; Wed, 25 Aug 2021 01:44:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIle7-0008K2-DE; Wed, 25 Aug 2021 01:40:19 -0400 Received: from ozlabs.org ([203.11.71.1]:40159) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIldz-0006DC-FK; Wed, 25 Aug 2021 01:40:18 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4GvZYx3Nv5z9sXN; Wed, 25 Aug 2021 15:40:05 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gibson.dropbear.id.au; s=201602; t=1629870005; bh=fTIV6O/E8oOGB3DFoJvFDohZhXBbyS42SGBT3XM9Fgk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kxAdymxrYFaMr6A1JpAHzhchigMWOhpH0R/mnerH3FLL691KtWpMPG/S75mKQnr3y AzHx2ImfzxcI8r7ALHhFav6DyYF6P4v+Cn8o7pNbPfki/B6clFnYzRDz6PPxuUsw8+ fh/jkBuvGMB1m9L6hKAiWdlyP/CNiFAV1/Pr24SI= Date: Wed, 25 Aug 2021 15:32:25 +1000 From: David Gibson To: Daniel Henrique Barboza Subject: Re: [PATCH v2 07/16] target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event Message-ID: References: <20210824163032.394099-1-danielhb413@gmail.com> <20210824163032.394099-8-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="AJP5abc6/0KC6yP0" Content-Disposition: inline In-Reply-To: <20210824163032.394099-8-danielhb413@gmail.com> Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --AJP5abc6/0KC6yP0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Aug 24, 2021 at 01:30:23PM -0300, Daniel Henrique Barboza wrote: > PM_RUN_INST_CMPL, instructions completed with the run latch set, is > the architected PowerISA v3.1 event defined with PMC4SEL =3D 0xFA. >=20 > Implement it by checking for the CTRL RUN bit before incrementing the > counter. >=20 > Signed-off-by: Daniel Henrique Barboza > --- > target/ppc/cpu.h | 3 +++ > target/ppc/power8_pmu.c | 25 ++++++++++++++++++++----- > 2 files changed, 23 insertions(+), 5 deletions(-) >=20 > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index e5df644a3c..60e5e1159a 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -358,6 +358,9 @@ typedef struct ppc_v3_pate_t { > #define MMCR1_PMC3SEL PPC_BITMASK(48, 55) > #define MMCR1_PMC4SEL PPC_BITMASK(56, 63) > =20 > +/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ > +#define CTRL_RUN PPC_BIT(63) > + > /* LPCR bits */ > #define LPCR_VPM0 PPC_BIT(0) > #define LPCR_VPM1 PPC_BIT(1) > diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c > index 311eaa358f..9154fca5fd 100644 > --- a/target/ppc/power8_pmu.c > +++ b/target/ppc/power8_pmu.c > @@ -131,10 +131,10 @@ void helper_store_mmcr0(CPUPPCState *env, target_ul= ong value) > } > } > =20 > -static bool pmc_counting_insns(CPUPPCState *env, int sprn) > +static bool pmc_counting_insns(CPUPPCState *env, int sprn, > + uint8_t event) > { > bool ret =3D false; > - uint8_t event; > =20 > if (sprn =3D=3D SPR_POWER_PMC5) { > return true; > @@ -156,8 +156,15 @@ static bool pmc_counting_insns(CPUPPCState *env, int= sprn) > return event =3D=3D 0x2 || event =3D=3D 0xFE; > case SPR_POWER_PMC2: > case SPR_POWER_PMC3: > - case SPR_POWER_PMC4: > return event =3D=3D 0x2; > + case SPR_POWER_PMC4: > + /* > + * Event 0xFA is the "instructions completed with run latch > + * set" event. Consider it as instruction counting event. > + * The caller is responsible for handling it separately > + * from PM_INST_CMPL. > + */ > + return event =3D=3D 0x2 || event =3D=3D 0xFA; > default: > break; > } > @@ -171,8 +178,16 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num= _insns) > int sprn; > =20 > for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC5; sprn++) { > - if (pmc_counting_insns(env, sprn)) { > - env->spr[sprn] +=3D num_insns; > + uint8_t event =3D get_PMC_event(env, sprn); > + > + if (pmc_counting_insns(env, sprn, event)) { > + if (sprn =3D=3D SPR_POWER_PMC4 && event =3D=3D 0xFA) { > + if (env->spr[SPR_CTRL] & CTRL_RUN) { > + env->spr[SPR_POWER_PMC4] +=3D num_insns; This is only correct if changes to CTRL force a new translation block. Is that true at the moment? > + } > + } else { > + env->spr[sprn] +=3D num_insns; > + } > } > } > } --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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