From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D9CC433FE for ; Tue, 7 Sep 2021 02:16:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49E8A6109F for ; Tue, 7 Sep 2021 02:16:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 49E8A6109F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNQf5-0006hb-9F for qemu-devel@archiver.kernel.org; Mon, 06 Sep 2021 22:16:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNQar-0002op-H6; Mon, 06 Sep 2021 22:12:13 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:39849) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNQao-0000uq-V9; Mon, 06 Sep 2021 22:12:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gibson.dropbear.id.au; s=201602; t=1630980726; bh=B5yk7uobyQj92jmtnbSULoVL79aQ6TGCYmpnRJRfhC4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fe7o/VDuSgeJ/IXtYVvIjqmqwpV2xhNrnZ6QlvDgxLFtWKxoMWKQdAhZ1gNoQzqtP 2QF44CehWHkohoUmE4eca07QGKR0La24N+WioXzJsbMfurjM1y96h0jMjt/HauYDru Rg+TzWWJ0TPmxH0REbZp2tIzi7CNlYiell5t4JMY= Received: by ozlabs.org (Postfix, from userid 1007) id 4H3TKy1Qkwz9sW8; Tue, 7 Sep 2021 12:12:06 +1000 (AEST) Date: Tue, 7 Sep 2021 11:27:04 +1000 From: David Gibson To: Daniel Henrique Barboza Subject: Re: [PATCH v3 01/15] target/ppc: add user read functions for MMCR0 and MMCR2 Message-ID: References: <20210903203116.80628-1-danielhb413@gmail.com> <20210903203116.80628-2-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="3J9xu6EKgm6n5/Zj" Content-Disposition: inline In-Reply-To: <20210903203116.80628-2-danielhb413@gmail.com> Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gustavo Romero , Gustavo Romero , richard.henderson@linaro.org, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, matheus.ferst@eldorado.org.br Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --3J9xu6EKgm6n5/Zj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 03, 2021 at 05:31:02PM -0300, Daniel Henrique Barboza wrote: > From: Gustavo Romero >=20 > We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+ > emulation and following PowerISA v3.1. >=20 > Let's start by handling the user read of UMMCR0 and UMMCR2. According to > PowerISA 3.1 these registers omit some of its bits from userspace. >=20 > CC: Gustavo Romero > Signed-off-by: Gustavo Romero > Signed-off-by: Daniel Henrique Barboza LGTM except for one nit... [snip] > +void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn) > +{ > + TCGv t0 =3D tcg_temp_new(); > + > + /* > + * On read, filter out all bits that are not FCnP0 bits. > + * When MMCR0[PMCC] is set to 0b10 or 0b11, providing > + * problem state programs read/write access to MMCR2, > + * only the FCnP0 bits can be accessed. All other bits are > + * not changed when mtspr is executed in problem state, and > + * all other bits return 0s when mfspr is executed in problem > + * state, according to ISA v3.1, section 10.4.6 Monitor Mode > + * Control Register 2, p. 1316, third paragraph. > + */ > + gen_load_spr(t0, SPR_POWER_MMCR2); > + tcg_gen_andi_tl(t0, t0, 0x4020100804020000UL); A #define for this mask... and #defines with meaningful names for the various bits it includes would be nice. > + tcg_gen_mov_tl(cpu_gpr[gprn], t0); > + > + tcg_temp_free(t0); > +} > + > #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) > void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) > { --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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