From: David Gibson <david@gibson.dropbear.id.au>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Maarten Koning" <maarten.koning@windriver.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Greg Kurz" <groug@kaod.org>, qemu-ppc <qemu-ppc@nongnu.org>,
"Cédric Le Goater" <clg@kaod.org>
Subject: Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset
Date: Mon, 27 Sep 2021 14:30:39 +1000 [thread overview]
Message-ID: <YVFI78c5xctdjEOC@yekko> (raw)
In-Reply-To: <CAEUhbmVn3VeGCV25jSXk4G6CRfFuBCX+wFbFKZNPoNKPakEZWA@mail.gmail.com>
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On Thu, Sep 23, 2021 at 01:33:44PM +0800, Bin Meng wrote:
> On Tue, Sep 21, 2021 at 4:13 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >
> > On 9/21/21 05:25, David Gibson wrote:
> > > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> > >> The reset value of IPIDR should be zero for Freescale chipset, per
> > >> the following 2 manuals I checked:
> > >>
> > >> - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> > >> - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
> > >>
> > >> Currently it is set to 1, which leaves the IPI enabled on core 0
> > >> after power-on reset. Such may cause unexpected interrupt to be
> > >> delivered to core 0 if the IPI is triggered from core 0 to other
> > >> cores later.
> > >>
> > >> Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
> > >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
> > >> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > >
> > > Since these patches are very simple and look sensible, I've applied
> > > them to ppc-for-6.2.
> > >
> > > However, you should note that Greg and I are both moving into other
> > > areas and don't have much capacity for ppc maintainership any more.
> > > Therefore I'll shortly be sending some MAINTAINERS updates moving
> > > openpic (amongst other things) to "Orphan" status.
> >
> > I'm not trying to force Bin to become (yet) another maintainer,
> > but from his previous contributions, he demonstrated a very good
> > knowledge of embedded PowerPC ISA & chipsets, his patches have good
> > quality and description, and he is consistent over time in his
> > contributions. So if he is interested, I'd vouch for him as a
> > maintainer for embedded ppc. Now up to him, his time and/or employer :)
> >
>
> Thanks Philippe for the offer.
>
> David, is this the whole PowerPC domain will become un-maintained
> soon, or is this just openpic and a few other things like a subset of
> PowerPC?
Essentially it's all of PowerPC, though we hope to make it a gradual
transition, rather than us dumping everything all at once. We're
starting off with offloading the smaller sub-platforms, including
e500.
> I got extensive working experience on Freescale/AMCC PowerPC chipset
> in the past, but I never touched anything on the Mac stuff with IBM
> chip. And I am not sure if I have enough time to do the work :(
I'm not suggesting you take over all of ppc. However, if you could
take e500, that could prevent it from being orphaned. My latest spin
of these maintainers changes moves the openpic_kvm.c file under e500
as well, since that seems to be the only user. The rest of openpic.c
is moving to the Mac platforms, maintainer by Mark Cave-Ayland.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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prev parent reply other threads:[~2021-09-27 4:39 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-18 3:26 [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset Bin Meng
2021-09-18 3:26 ` [RESEND PATCH 2/3] hw/intc: openpic: Drop Raven related codes Bin Meng
2021-09-18 3:26 ` [RESEND PATCH 3/3] hw/intc: openpic: Clean up the styles Bin Meng
2021-09-21 3:25 ` [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset David Gibson
2021-09-21 8:13 ` Philippe Mathieu-Daudé
2021-09-21 9:31 ` David Gibson
2021-09-23 5:33 ` Bin Meng
2021-09-27 4:30 ` David Gibson [this message]
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