[RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[Bin Meng]

The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:

- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)

Currently it is set to 1, which leaves the IPI enabled on core 0
after power-on reset. Such may cause unexpected interrupt to be
delivered to core 0 if the IPI is triggered from core 0 to other
cores later.

Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/intc/openpic.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 9b4c17854d..2790c6710a 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -1276,6 +1276,15 @@ static void openpic_reset(DeviceState *d)
             break;
         }
 
+        /* Mask all IPI interrupts for Freescale OpenPIC */
+        if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) ||
+            (opp->model == OPENPIC_MODEL_FSL_MPIC_42)) {
+            if (i >= opp->irq_ipi0 && i < opp->irq_tim0) {
+                write_IRQreg_idr(opp, i, 0);
+                continue;
+            }
+        }
+
         write_IRQreg_idr(opp, i, opp->idr_reset);
     }
     /* Initialise IRQ destinations */
-- 
2.25.1

[RESEND PATCH 2/3] hw/intc: openpic: Drop Raven related codes

[Bin Meng]

There is no machine that uses Motorola MCP750 (aka Raven) model.
Drop the related codes.

While we are here, drop the mentioning of Intel GW80314 I/O
companion chip in the comments as it has been obsolete for years,
and correct a typo too.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/ppc/openpic.h | 16 ----------------
 hw/intc/openpic.c        | 28 +---------------------------
 2 files changed, 1 insertion(+), 43 deletions(-)

diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h
index 74ff44bff0..f89802a15c 100644
--- a/include/hw/ppc/openpic.h
+++ b/include/hw/ppc/openpic.h
@@ -21,7 +21,6 @@ enum {
 
 typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
 
-#define OPENPIC_MODEL_RAVEN       0
 #define OPENPIC_MODEL_FSL_MPIC_20 1
 #define OPENPIC_MODEL_FSL_MPIC_42 2
 #define OPENPIC_MODEL_KEYLARGO    3
@@ -32,13 +31,6 @@ typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
 #define OPENPIC_MAX_IRQ     (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
                              OPENPIC_MAX_TMR)
 
-/* Raven */
-#define RAVEN_MAX_CPU      2
-#define RAVEN_MAX_EXT     48
-#define RAVEN_MAX_IRQ     64
-#define RAVEN_MAX_TMR      OPENPIC_MAX_TMR
-#define RAVEN_MAX_IPI      OPENPIC_MAX_IPI
-
 /* KeyLargo */
 #define KEYLARGO_MAX_CPU  4
 #define KEYLARGO_MAX_EXT  64
@@ -49,14 +41,6 @@ typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
 /* Timers don't exist but this makes the code happy... */
 #define KEYLARGO_TMR_IRQ  (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
 
-/* Interrupt definitions */
-#define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
-#define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
-#define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
-#define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
-/* First doorbell IRQ */
-#define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
-
 typedef struct FslMpicInfo {
     int max_ext;
 } FslMpicInfo;
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 2790c6710a..23eafb32bd 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -25,12 +25,8 @@
 /*
  *
  * Based on OpenPic implementations:
- * - Intel GW80314 I/O companion chip developer's manual
  * - Motorola MPC8245 & MPC8540 user manuals.
- * - Motorola MCP750 (aka Raven) programmer manual.
- * - Motorola Harrier programmer manuel
- *
- * Serial interrupts, as implemented in Raven chipset are not supported yet.
+ * - Motorola Harrier programmer manual
  *
  */
 
@@ -1564,28 +1560,6 @@ static void openpic_realize(DeviceState *dev, Error **errp)
 
         break;
 
-    case OPENPIC_MODEL_RAVEN:
-        opp->nb_irqs = RAVEN_MAX_EXT;
-        opp->vid = VID_REVISION_1_3;
-        opp->vir = VIR_GENERIC;
-        opp->vector_mask = 0xFF;
-        opp->tfrr_reset = 4160000;
-        opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
-        opp->idr_reset = 0;
-        opp->max_irq = RAVEN_MAX_IRQ;
-        opp->irq_ipi0 = RAVEN_IPI_IRQ;
-        opp->irq_tim0 = RAVEN_TMR_IRQ;
-        opp->brr1 = -1;
-        opp->mpic_mode_mask = GCR_MODE_MIXED;
-
-        if (opp->nb_cpus != 1) {
-            error_setg(errp, "Only UP supported today");
-            return;
-        }
-
-        map_list(opp, list_le, &list_count);
-        break;
-
     case OPENPIC_MODEL_KEYLARGO:
         opp->nb_irqs = KEYLARGO_MAX_EXT;
         opp->vid = VID_REVISION_1_2;
-- 
2.25.1

[RESEND PATCH 3/3] hw/intc: openpic: Clean up the styles

[Bin Meng]

Correct the multi-line comment format. No functional changes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

---

 include/hw/ppc/openpic.h |  9 ++++---
 hw/intc/openpic.c        | 55 +++++++++++++++++++++++++---------------
 2 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h
index f89802a15c..ebdaf8a493 100644
--- a/include/hw/ppc/openpic.h
+++ b/include/hw/ppc/openpic.h
@@ -51,7 +51,8 @@ typedef enum IRQType {
     IRQ_TYPE_FSLSPECIAL,    /* FSL timer/IPI interrupt, edge, no polarity */
 } IRQType;
 
-/* Round up to the nearest 64 IRQs so that the queue length
+/*
+ * Round up to the nearest 64 IRQs so that the queue length
  * won't change when moving between 32 and 64 bit hosts.
  */
 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
@@ -101,8 +102,10 @@ typedef struct OpenPICTimer {
     bool                  qemu_timer_active; /* Is the qemu_timer is running? */
     struct QEMUTimer     *qemu_timer;
     struct OpenPICState  *opp;          /* Device timer is part of. */
-    /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
-       current_count written or read, only defined if qemu_timer_active. */
+    /*
+     * The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
+     * current_count written or read, only defined if qemu_timer_active.
+     */
     uint64_t              origin_time;
 } OpenPICTimer;
 
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 23eafb32bd..49504e740f 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -47,7 +47,7 @@
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 
-//#define DEBUG_OPENPIC
+/* #define DEBUG_OPENPIC */
 
 #ifdef DEBUG_OPENPIC
 static const int debug_openpic = 1;
@@ -118,7 +118,8 @@ static FslMpicInfo fsl_mpic_42 = {
 #define ILR_INTTGT_CINT   0x01 /* critical */
 #define ILR_INTTGT_MCP    0x02 /* machine check */
 
-/* The currently supported INTTGT values happen to be the same as QEMU's
+/*
+ * The currently supported INTTGT values happen to be the same as QEMU's
  * openpic output codes, but don't depend on this.  The output codes
  * could change (unlikely, but...) or support could be added for
  * more INTTGT values.
@@ -177,10 +178,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
                                        uint32_t val, int idx);
 static void openpic_reset(DeviceState *d);
 
-/* Convert between openpic clock ticks and nanosecs.  In the hardware the clock
-   frequency is driven by board inputs to the PIC which the PIC would then
-   divide by 4 or 8.  For now hard code to 25MZ.
-*/
+/*
+ * Convert between openpic clock ticks and nanosecs.  In the hardware the clock
+ * frequency is driven by board inputs to the PIC which the PIC would then
+ * divide by 4 or 8.  For now hard code to 25MZ.
+ */
 #define OPENPIC_TIMER_FREQ_MHZ 25
 #define OPENPIC_TIMER_NS_PER_TICK (1000 / OPENPIC_TIMER_FREQ_MHZ)
 static inline uint64_t ns_to_ticks(uint64_t ns)
@@ -253,7 +255,8 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
                 __func__, src->output, n_IRQ, active, was_active,
                 dst->outputs_active[src->output]);
 
-        /* On Freescale MPIC, critical interrupts ignore priority,
+        /*
+         * On Freescale MPIC, critical interrupts ignore priority,
          * IACK, EOI, etc.  Before MPIC v4.1 they also ignore
          * masking.
          */
@@ -276,7 +279,8 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
 
     priority = IVPR_PRIORITY(src->ivpr);
 
-    /* Even if the interrupt doesn't have enough priority,
+    /*
+     * Even if the interrupt doesn't have enough priority,
      * it is still raised, in case ctpr is lowered later.
      */
     if (active) {
@@ -408,7 +412,8 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
         }
 
         if (src->output != OPENPIC_OUTPUT_INT) {
-            /* Edge-triggered interrupts shouldn't be used
+            /*
+             * Edge-triggered interrupts shouldn't be used
              * with non-INT delivery, but just in case,
              * try to make it do something sane rather than
              * cause an interrupt storm.  This is close to
@@ -501,7 +506,8 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
 {
     uint32_t mask;
 
-    /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
+    /*
+     * NOTE when implementing newer FSL MPIC models: starting with v4.0,
      * the polarity bit is read-only on internal interrupts.
      */
     mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
@@ -511,7 +517,8 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
     opp->src[n_IRQ].ivpr =
         (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
 
-    /* For FSL internal interrupts, The sense bit is reserved and zero,
+    /*
+     * For FSL internal interrupts, The sense bit is reserved and zero,
      * and the interrupt is always level-triggered.  Timers and IPIs
      * have no sense or polarity bits, and are edge-triggered.
      */
@@ -695,16 +702,20 @@ static void qemu_timer_cb(void *opaque)
     openpic_set_irq(opp, n_IRQ, 0);
 }
 
-/* If enabled is true, arranges for an interrupt to be raised val clocks into
-   the future, if enabled is false cancels the timer. */
+/*
+ * If enabled is true, arranges for an interrupt to be raised val clocks into
+ * the future, if enabled is false cancels the timer.
+ */
 static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
 {
     uint64_t ns = ticks_to_ns(val & ~TCCR_TOG);
-    /* A count of zero causes a timer to be set to expire immediately.  This
-       effectively stops the simulation since the timer is constantly expiring
-       which prevents guest code execution, so we don't honor that
-       configuration.  On real hardware, this situation would generate an
-       interrupt on every clock cycle if the interrupt was unmasked. */
+    /*
+     * A count of zero causes a timer to be set to expire immediately.  This
+     * effectively stops the simulation since the timer is constantly expiring
+     * which prevents guest code execution, so we don't honor that
+     * configuration.  On real hardware, this situation would generate an
+     * interrupt on every clock cycle if the interrupt was unmasked.
+     */
     if ((ns == 0) || !enabled) {
         tmr->qemu_timer_active = false;
         tmr->tccr = tmr->tccr & TCCR_TOG;
@@ -717,8 +728,10 @@ static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
     }
 }
 
-/* Returns the currrent tccr value, i.e., timer value (in clocks) with
-   appropriate TOG. */
+/*
+ * Returns the currrent tccr value, i.e., timer value (in clocks) with
+ * appropriate TOG.
+ */
 static uint64_t openpic_tmr_get_timer(OpenPICTimer *tmr)
 {
     uint64_t retval;
@@ -1309,7 +1322,7 @@ static void openpic_reset(DeviceState *d)
 typedef struct MemReg {
     const char             *name;
     MemoryRegionOps const  *ops;
-    hwaddr      start_addr;
+    hwaddr                  start_addr;
     ram_addr_t              size;
 } MemReg;
 
-- 
2.25.1

Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 2081 bytes --]

On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> The reset value of IPIDR should be zero for Freescale chipset, per
> the following 2 manuals I checked:
> 
> - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
> 
> Currently it is set to 1, which leaves the IPI enabled on core 0
> after power-on reset. Such may cause unexpected interrupt to be
> delivered to core 0 if the IPI is triggered from core 0 to other
> cores later.
> 
> Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Since these patches are very simple and look sensible, I've applied
them to ppc-for-6.2.

However, you should note that Greg and I are both moving into other
areas and don't have much capacity for ppc maintainership any more.
Therefore I'll shortly be sending some MAINTAINERS updates moving
openpic (amongst other things) to "Orphan" status.

> ---
> 
>  hw/intc/openpic.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
> index 9b4c17854d..2790c6710a 100644
> --- a/hw/intc/openpic.c
> +++ b/hw/intc/openpic.c
> @@ -1276,6 +1276,15 @@ static void openpic_reset(DeviceState *d)
>              break;
>          }
>  
> +        /* Mask all IPI interrupts for Freescale OpenPIC */
> +        if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) ||
> +            (opp->model == OPENPIC_MODEL_FSL_MPIC_42)) {
> +            if (i >= opp->irq_ipi0 && i < opp->irq_tim0) {
> +                write_IRQreg_idr(opp, i, 0);
> +                continue;
> +            }
> +        }
> +
>          write_IRQreg_idr(opp, i, opp->idr_reset);
>      }
>      /* Initialise IRQ destinations */

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[Philippe Mathieu-Daudé]

On 9/21/21 05:25, David Gibson wrote:
> On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
>> The reset value of IPIDR should be zero for Freescale chipset, per
>> the following 2 manuals I checked:
>>
>> - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
>> - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
>>
>> Currently it is set to 1, which leaves the IPI enabled on core 0
>> after power-on reset. Such may cause unexpected interrupt to be
>> delivered to core 0 if the IPI is triggered from core 0 to other
>> cores later.
>>
>> Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
>> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> 
> Since these patches are very simple and look sensible, I've applied
> them to ppc-for-6.2.
> 
> However, you should note that Greg and I are both moving into other
> areas and don't have much capacity for ppc maintainership any more.
> Therefore I'll shortly be sending some MAINTAINERS updates moving
> openpic (amongst other things) to "Orphan" status.

I'm not trying to force Bin to become (yet) another maintainer,
but from his previous contributions, he demonstrated a very good
knowledge of embedded PowerPC ISA & chipsets, his patches have good
quality and description, and he is consistent over time in his
contributions. So if he is interested, I'd vouch for him as a
maintainer for embedded ppc. Now up to him, his time and/or employer :)

Regards,

Phil.

Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 1929 bytes --]

On Tue, Sep 21, 2021 at 10:13:36AM +0200, Philippe Mathieu-Daudé wrote:
> On 9/21/21 05:25, David Gibson wrote:
> > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> > > The reset value of IPIDR should be zero for Freescale chipset, per
> > > the following 2 manuals I checked:
> > > 
> > > - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> > > - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
> > > 
> > > Currently it is set to 1, which leaves the IPI enabled on core 0
> > > after power-on reset. Such may cause unexpected interrupt to be
> > > delivered to core 0 if the IPI is triggered from core 0 to other
> > > cores later.
> > > 
> > > Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
> > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
> > > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > 
> > Since these patches are very simple and look sensible, I've applied
> > them to ppc-for-6.2.
> > 
> > However, you should note that Greg and I are both moving into other
> > areas and don't have much capacity for ppc maintainership any more.
> > Therefore I'll shortly be sending some MAINTAINERS updates moving
> > openpic (amongst other things) to "Orphan" status.
> 
> I'm not trying to force Bin to become (yet) another maintainer,
> but from his previous contributions, he demonstrated a very good
> knowledge of embedded PowerPC ISA & chipsets, his patches have good
> quality and description, and he is consistent over time in his
> contributions. So if he is interested, I'd vouch for him as a
> maintainer for embedded ppc. Now up to him, his time and/or employer
> :)

Ok, works for me if he's interested.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[Bin Meng]

On Tue, Sep 21, 2021 at 4:13 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 9/21/21 05:25, David Gibson wrote:
> > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> >> The reset value of IPIDR should be zero for Freescale chipset, per
> >> the following 2 manuals I checked:
> >>
> >> - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> >> - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
> >>
> >> Currently it is set to 1, which leaves the IPI enabled on core 0
> >> after power-on reset. Such may cause unexpected interrupt to be
> >> delivered to core 0 if the IPI is triggered from core 0 to other
> >> cores later.
> >>
> >> Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
> >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
> >> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> >
> > Since these patches are very simple and look sensible, I've applied
> > them to ppc-for-6.2.
> >
> > However, you should note that Greg and I are both moving into other
> > areas and don't have much capacity for ppc maintainership any more.
> > Therefore I'll shortly be sending some MAINTAINERS updates moving
> > openpic (amongst other things) to "Orphan" status.
>
> I'm not trying to force Bin to become (yet) another maintainer,
> but from his previous contributions, he demonstrated a very good
> knowledge of embedded PowerPC ISA & chipsets, his patches have good
> quality and description, and he is consistent over time in his
> contributions. So if he is interested, I'd vouch for him as a
> maintainer for embedded ppc. Now up to him, his time and/or employer :)
>

Thanks Philippe for the offer.

David, is this the whole PowerPC domain will become un-maintained
soon, or is this just openpic and a few other things like a subset of
PowerPC?

I got extensive working experience on Freescale/AMCC PowerPC chipset
in the past, but I never touched anything on the Mac stuff with IBM
chip. And I am not sure if I have enough time to do the work :(

Regards,
Bin

Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 2976 bytes --]

On Thu, Sep 23, 2021 at 01:33:44PM +0800, Bin Meng wrote:
> On Tue, Sep 21, 2021 at 4:13 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >
> > On 9/21/21 05:25, David Gibson wrote:
> > > On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> > >> The reset value of IPIDR should be zero for Freescale chipset, per
> > >> the following 2 manuals I checked:
> > >>
> > >> - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> > >> - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
> > >>
> > >> Currently it is set to 1, which leaves the IPI enabled on core 0
> > >> after power-on reset. Such may cause unexpected interrupt to be
> > >> delivered to core 0 if the IPI is triggered from core 0 to other
> > >> cores later.
> > >>
> > >> Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
> > >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
> > >> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > >
> > > Since these patches are very simple and look sensible, I've applied
> > > them to ppc-for-6.2.
> > >
> > > However, you should note that Greg and I are both moving into other
> > > areas and don't have much capacity for ppc maintainership any more.
> > > Therefore I'll shortly be sending some MAINTAINERS updates moving
> > > openpic (amongst other things) to "Orphan" status.
> >
> > I'm not trying to force Bin to become (yet) another maintainer,
> > but from his previous contributions, he demonstrated a very good
> > knowledge of embedded PowerPC ISA & chipsets, his patches have good
> > quality and description, and he is consistent over time in his
> > contributions. So if he is interested, I'd vouch for him as a
> > maintainer for embedded ppc. Now up to him, his time and/or employer :)
> >
> 
> Thanks Philippe for the offer.
> 
> David, is this the whole PowerPC domain will become un-maintained
> soon, or is this just openpic and a few other things like a subset of
> PowerPC?

Essentially it's all of PowerPC, though we hope to make it a gradual
transition, rather than us dumping everything all at once.  We're
starting off with offloading the smaller sub-platforms, including
e500.

> I got extensive working experience on Freescale/AMCC PowerPC chipset
> in the past, but I never touched anything on the Mac stuff with IBM
> chip. And I am not sure if I have enough time to do the work :(

I'm not suggesting you take over all of ppc.  However, if you could
take e500, that could prevent it from being orphaned.  My latest spin
of these maintainers changes moves the openpic_kvm.c file under e500
as well, since that seems to be the only user.  The rest of openpic.c
is moving to the Mac platforms, maintainer by Mark Cave-Ayland.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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