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Tue, 2 Nov 2021 10:35:49 -0400 (EDT) Date: Tue, 2 Nov 2021 15:35:47 +0100 From: Klaus Jensen To: Lukasz Maniak Subject: Re: [PATCH 09/15] hw/nvme: Implement the Function Level Reset Message-ID: References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> <20211007162406.1920374-10-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="sEIzPrjcEGbR8ZNc" Content-Disposition: inline In-Reply-To: <20211007162406.1920374-10-lukasz.maniak@linux.intel.com> Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , =?utf-8?Q?=C5=81ukasz?= Gieryk , qemu-devel@nongnu.org, qemu-block@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --sEIzPrjcEGbR8ZNc Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Oct 7 18:24, Lukasz Maniak wrote: > From: =C5=81ukasz Gieryk >=20 > This patch implements the FLR, a feature currently not implemented for > the Nvme device, while listed as a mandatory ("shall") in the 1.4 spec. >=20 > The implementation reuses FLR-related building blocks defined for the > pci-bridge module, and follows the same logic: > - FLR capability is advertised in the PCIE config, > - custom pci_write_config callback detects a write to the trigger > register and performs the PCI reset, > - which, eventually, calls the custom dc->reset handler. >=20 > Depending on reset type, parts of the state should (or should not) be > cleared. To distinguish the type of reset, an additional parameter is > passed to the reset function. >=20 > This patch also enables advertisement of the Power Management PCI > capability. The main reason behind it is to announce the no_soft_reset=3D1 > bit, to signal SR/IOV support where each VF can be reset individually. >=20 > The implementation purposedly ignores writes to the PMCS.PS register, > as even such na=C3=AFve behavior is enough to correctly handle the D3->D0 > transition. >=20 > It=E2=80=99s worth to note, that the power state transition back to to D3= , with > all the corresponding side effects, wasn't and stil isn't handled > properly. >=20 > Signed-off-by: =C5=81ukasz Gieryk Reviewed-by: Klaus Jensen --sEIzPrjcEGbR8ZNc Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmGBTMIACgkQTeGvMW1P DenHSgf/cUX/oJrC1SdGJSm0keuHuqFsBXipncP8oERH/TK5CI8KPFzlUod70cCR 8tY4BTHlq3JXONoOSrH/DVpKMTv/Adu9MY8jh+NG9C1jGAK2OcF/RRffGCY6Yawh bU1usyTVsb8axrK5n2u6LXUiehjwJmiJvbg079k9glmiCGZy5z94Y/ExJVGfUEpX 0wHTboUkK/9Q5gAf5lwAII0rMuB1LozUm5v2lC6U9C/cQU8Fl6XA8Gz9jIchmZ2R wfqgGzpaqu3BLGt8j5IWUEeDXhaYllAueLEbzqLxY5D5itEOeednirSvqTyyDd9d FGE2TOwiNd+RguwtdMQYEPU5X6yynw== =9yVB -----END PGP SIGNATURE----- --sEIzPrjcEGbR8ZNc--