From: David Gibson <david@gibson.dropbear.id.au>
To: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org, clg@kaod.org
Subject: Re: [PATCH v8 03/10] target/ppc: PMU: update counters on PMCs r/w
Date: Fri, 26 Nov 2021 13:24:00 +1100 [thread overview]
Message-ID: <YaBFQGHNpesVcIti@yekko> (raw)
In-Reply-To: <20211125150817.573204-4-danielhb413@gmail.com>
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On Thu, Nov 25, 2021 at 12:08:10PM -0300, Daniel Henrique Barboza wrote:
> Calling pmu_update_cycles() on every PMC read/write operation ensures
> that the values being fetched are up to date with the current PMU state.
>
> In theory we can get away by just trapping PMCs reads, but we're going
> to trap PMC writes to deal with counter overflow logic later on. Let's
> put the required wiring for that and make our lives a bit easier in the
> next patches.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/cpu_init.c | 12 ++++++------
> target/ppc/helper.h | 2 ++
> target/ppc/power8-pmu-regs.c.inc | 29 +++++++++++++++++++++++++++--
> target/ppc/power8-pmu.c | 14 ++++++++++++++
> target/ppc/spr_tcg.h | 2 ++
> 5 files changed, 51 insertions(+), 8 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e0b6fe4057..a7f47ec322 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -6833,27 +6833,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
> KVM_REG_PPC_MMCRA, 0x00000000);
> spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_PMC, &spr_write_PMC,
> KVM_REG_PPC_PMC1, 0x00000000);
> spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_PMC, &spr_write_PMC,
> KVM_REG_PPC_PMC2, 0x00000000);
> spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_PMC, &spr_write_PMC,
> KVM_REG_PPC_PMC3, 0x00000000);
> spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_PMC, &spr_write_PMC,
> KVM_REG_PPC_PMC4, 0x00000000);
> spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_PMC, &spr_write_PMC,
> KVM_REG_PPC_PMC5, 0x00000000);
> spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_PMC, &spr_write_PMC,
> KVM_REG_PPC_PMC6, 0x00000000);
> spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
> SPR_NOACCESS, SPR_NOACCESS,
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index ea60a7493c..d7567f75b4 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -21,6 +21,8 @@ DEF_HELPER_1(hrfid, void, env)
> DEF_HELPER_2(store_lpcr, void, env, tl)
> DEF_HELPER_2(store_pcr, void, env, tl)
> DEF_HELPER_2(store_mmcr0, void, env, tl)
> +DEF_HELPER_3(store_pmc, void, env, i32, i64)
> +DEF_HELPER_2(read_pmc, tl, env, i32)
> #endif
> DEF_HELPER_1(check_tlb_flush_local, void, env)
> DEF_HELPER_1(check_tlb_flush_global, void, env)
> diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
> index fbb8977641..f0c9cc343b 100644
> --- a/target/ppc/power8-pmu-regs.c.inc
> +++ b/target/ppc/power8-pmu-regs.c.inc
> @@ -181,13 +181,23 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
> tcg_temp_free(masked_gprn);
> }
>
> +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv_i32 t_sprn = tcg_const_i32(sprn);
> +
> + gen_icount_io_start(ctx);
> + gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
> +
> + tcg_temp_free_i32(t_sprn);
> +}
> +
> void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
> {
> if (!spr_groupA_read_allowed(ctx)) {
> return;
> }
>
> - spr_read_ureg(ctx, gprn, sprn);
> + spr_read_PMC(ctx, gprn, sprn + 0x10);
> }
>
> void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
> @@ -206,13 +216,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
> spr_read_PMC14_ureg(ctx, gprn, sprn);
> }
>
> +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t_sprn = tcg_const_i32(sprn);
> +
> + gen_icount_io_start(ctx);
> + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
> +
> + tcg_temp_free_i32(t_sprn);
> +}
> +
> void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
> {
> if (!spr_groupA_write_allowed(ctx)) {
> return;
> }
>
> - spr_write_ureg(ctx, sprn, gprn);
> + spr_write_PMC(ctx, sprn + 0x10, gprn);
> }
>
> void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
> @@ -280,4 +300,9 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
> {
> spr_write_generic(ctx, sprn, gprn);
> }
> +
> +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
> +{
> + spr_write_generic(ctx, sprn, gprn);
> +}
> #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
> index 47932ded4f..5f2623aa25 100644
> --- a/target/ppc/power8-pmu.c
> +++ b/target/ppc/power8-pmu.c
> @@ -145,6 +145,20 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
> }
> }
>
> +target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
> +{
> + pmu_update_cycles(env);
> +
> + return env->spr[sprn];
> +}
> +
> +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
> +{
> + pmu_update_cycles(env);
> +
> + env->spr[sprn] = value;
> +}
> +
> static void fire_PMC_interrupt(PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
> index eb1d0c2bf0..1e79a0522a 100644
> --- a/target/ppc/spr_tcg.h
> +++ b/target/ppc/spr_tcg.h
> @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
> void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
> void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
> void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
> +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
> void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
> void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
> void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
> @@ -35,6 +36,7 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gprn);
> void spr_read_ureg(DisasContext *ctx, int gprn, int sprn);
> void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn);
> void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn);
> +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn);
> void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn);
> void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn);
> void spr_read_tbl(DisasContext *ctx, int gprn, int sprn);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2021-11-26 11:16 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 15:08 [PATCH v8 00/10] PMU-EBB support for PPC64 TCG Daniel Henrique Barboza
2021-11-25 15:08 ` [PATCH v8 01/10] target/ppc: introduce PMUEventType and PMU overflow timers Daniel Henrique Barboza
2021-11-25 15:08 ` [PATCH v8 02/10] target/ppc: PMU basic cycle count for pseries TCG Daniel Henrique Barboza
2021-11-26 2:17 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 03/10] target/ppc: PMU: update counters on PMCs r/w Daniel Henrique Barboza
2021-11-26 2:24 ` David Gibson [this message]
2021-11-25 15:08 ` [PATCH v8 04/10] target/ppc: PMU: update counters on MMCR1 write Daniel Henrique Barboza
2021-11-26 2:24 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 05/10] target/ppc: enable PMU counter overflow with cycle events Daniel Henrique Barboza
2021-11-29 3:41 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 06/10] target/ppc: enable PMU instruction count Daniel Henrique Barboza
2021-11-29 4:36 ` David Gibson
2021-11-30 22:24 ` Daniel Henrique Barboza
2021-11-30 23:52 ` David Gibson
2021-12-01 13:12 ` Daniel Henrique Barboza
2021-12-02 1:23 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 07/10] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event Daniel Henrique Barboza
2021-11-30 0:33 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 08/10] PPC64/TCG: Implement 'rfebb' instruction Daniel Henrique Barboza
2021-11-30 4:11 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 09/10] target/ppc: PMU Event-Based exception support Daniel Henrique Barboza
2021-11-30 4:15 ` David Gibson
2021-11-25 15:08 ` [PATCH v8 10/10] target/ppc/excp_helper.c: EBB handling adjustments Daniel Henrique Barboza
2021-11-30 4:17 ` David Gibson
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