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From: David Gibson <david@gibson.dropbear.id.au>
To: Fabiano Rosas <farosas@linux.ibm.com>
Cc: richard.henderson@linaro.org, danielhb413@gmail.com,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org
Subject: Re: [PATCH 1/8] target/ppc: 405: Add missing MSR bits to msr_mask
Date: Tue, 11 Jan 2022 13:07:54 +1100	[thread overview]
Message-ID: <YdzmepZtTxm9Qap+@yekko> (raw)
In-Reply-To: <Ydzlnpk8GgUBs5ZY@yekko>

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On Tue, Jan 11, 2022 at 01:04:14PM +1100, David Gibson wrote:
> On Mon, Jan 10, 2022 at 03:15:39PM -0300, Fabiano Rosas wrote:
> > Some bits described in the user manual are missing from msr_mask. Add
> > them.
> > 
> > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> > ---
> >  target/ppc/cpu_init.c | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> > index e30e86fe9d..a50ddaeaae 100644
> > --- a/target/ppc/cpu_init.c
> > +++ b/target/ppc/cpu_init.c
> > @@ -2535,15 +2535,19 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> >                         PPC_MEM_SYNC | PPC_MEM_EIEIO |
> >                         PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
> >                         PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
> > -    pcc->msr_mask = (1ull << MSR_POW) |
> > +    pcc->msr_mask = (1ull << MSR_AP) |
> > +                    (1ull << MSR_POW) |
> 
> If I'm looking at things correctly, the "MSR_POW" bit on 405 is
> actually called "MSR_WE", which appears related, but not quite
> identical.  I think it would be good to introduce a new define to get
> it a name matching the user manual.

Also, it looks like this is still missing the MSR[APE] bit (in the
same place as the MSR_KEY bit on 603e).

> >                      (1ull << MSR_CE) |
> >                      (1ull << MSR_EE) |
> >                      (1ull << MSR_PR) |
> >                      (1ull << MSR_FP) |
> > +                    (1ull << MSR_ME) |
> >                      (1ull << MSR_DWE) |
> >                      (1ull << MSR_DE) |
> > +                    (1ull << MSR_FE1) |
> >                      (1ull << MSR_IR) |
> >                      (1ull << MSR_DR);
> > +
> >      pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
> >      pcc->excp_model = POWERPC_EXCP_40x;
> >      pcc->bus_model = PPC_FLAGS_INPUT_405;
> 



-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2022-01-11  2:34 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-10 18:15 [PATCH 0/8] target/ppc: powerpc_excp improvements [40x] (3/n) Fabiano Rosas
2022-01-10 18:15 ` [PATCH 1/8] target/ppc: 405: Add missing MSR bits to msr_mask Fabiano Rosas
2022-01-11  2:04   ` David Gibson
2022-01-11  2:07     ` David Gibson [this message]
2022-01-17 21:12   ` Fabiano Rosas
2022-01-18  8:40     ` David Gibson
2022-01-10 18:15 ` [PATCH 2/8] target/ppc: 405: Add missing exception handlers Fabiano Rosas
2022-01-11  2:10   ` David Gibson
2022-01-14 21:46     ` Fabiano Rosas
2022-01-15  7:05       ` David Gibson
2022-01-10 18:15 ` [PATCH 3/8] target/ppc: Introduce powerpc_excp_40x Fabiano Rosas
2022-01-11  2:20   ` David Gibson
2022-01-10 18:15 ` [PATCH 4/8] squash " Fabiano Rosas
2022-01-10 18:51   ` BALATON Zoltan
2022-01-10 19:00     ` Fabiano Rosas
2022-01-10 18:15 ` [PATCH 5/8] target/ppc: 405: Critical exceptions cleanup Fabiano Rosas
2022-01-11  2:26   ` David Gibson
2022-01-10 18:15 ` [PATCH 6/8] target/ppc: 405: Machine check exception cleanup Fabiano Rosas
2022-01-11  2:26   ` David Gibson
2022-01-10 18:15 ` [PATCH 7/8] target/ppc: 405: External " Fabiano Rosas
2022-01-11  2:28   ` David Gibson
2022-01-10 18:15 ` [PATCH 8/8] target/ppc: 405: System call " Fabiano Rosas
2022-01-11  2:31   ` David Gibson
2022-01-11 12:48     ` Fabiano Rosas
2022-01-11  8:37 ` [PATCH 0/8] target/ppc: powerpc_excp improvements [40x] (3/n) Cédric Le Goater

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