Re: [PATCH v2 09/14] target/ppc: 405: Alignment exception cleanup

[David Gibson <david@gibson.dropbear.id.au>]

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On Tue, Jan 18, 2022 at 03:44:43PM -0300, Fabiano Rosas wrote:
> There is no DSISR in the 405. It uses DEAR which we already set
> earlier at ppc_cpu_do_unaligned_access.

Enabled specifically, I note, by env->mmu_model rather than
env->excp_model, which doesn't make a lot of sense.  Another cleanup
for later.

> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au

> ---
>  target/ppc/excp_helper.c | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 9a6f8365d6..d263f20002 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -474,13 +474,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>      case POWERPC_EXCP_EXTERNAL:  /* External input                           */
>          break;
>      case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
> -        /* Get rS/rD and rA from faulting opcode */
> -        /*
> -         * Note: the opcode fields will not be set properly for a
> -         * direct store load/store, but nobody cares as nobody
> -         * actually uses direct store segments.
> -         */
> -        env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
>          break;
>      case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
>          switch (env->error_code & ~0xF) {

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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