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Fri, 11 Feb 2022 02:55:21 -0500 (EST) Date: Fri, 11 Feb 2022 08:55:20 +0100 From: Klaus Jensen To: Lukasz Maniak Subject: Re: [PATCH v4 10/15] hw/nvme: Remove reg_size variable and update BAR0 size calculation Message-ID: References: <20220126171120.2939152-1-lukasz.maniak@linux.intel.com> <20220126171120.2939152-11-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Get4+DgDvqXD53HA" Content-Disposition: inline In-Reply-To: <20220126171120.2939152-11-lukasz.maniak@linux.intel.com> Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , =?utf-8?Q?=C5=81ukasz?= Gieryk , qemu-devel@nongnu.org, qemu-block@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --Get4+DgDvqXD53HA Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Jan 26 18:11, Lukasz Maniak wrote: > From: =C5=81ukasz Gieryk >=20 > The n->reg_size parameter unnecessarily splits the BAR0 size calculation > in two phases; removed to simplify the code. >=20 > With all the calculations done in one place, it seems the pow2ceil, > applied originally to reg_size, is unnecessary. The rounding should > happen as the last step, when BAR size includes Nvme registers, queue > registers, and MSIX-related space. >=20 > Finally, the size of the mmio memory region is extended to cover the 1st > 4KiB padding (see the map below). Access to this range is handled as > interaction with a non-existing queue and generates an error trace, so > actually nothing changes, while the reg_size variable is no longer needed. >=20 > -------------------- > | BAR0 | > -------------------- > [Nvme Registers ] > [Queues ] > [power-of-2 padding] - removed in this patch > [4KiB padding (1) ] > [MSIX TABLE ] > [4KiB padding (2) ] > [MSIX PBA ] > [power-of-2 padding] >=20 > Signed-off-by: =C5=81ukasz Gieryk > --- > hw/nvme/ctrl.c | 10 +++++----- > hw/nvme/nvme.h | 1 - > 2 files changed, 5 insertions(+), 6 deletions(-) >=20 > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > index 426507ca8a..40eb6bd1a8 100644 > --- a/hw/nvme/ctrl.c > +++ b/hw/nvme/ctrl.c > @@ -6372,9 +6372,6 @@ static void nvme_init_state(NvmeCtrl *n) > n->conf_ioqpairs =3D n->params.max_ioqpairs; > n->conf_msix_qsize =3D n->params.msix_qsize; > =20 > - /* add one to max_ioqpairs to account for the admin queue pair */ > - n->reg_size =3D pow2ceil(sizeof(NvmeBar) + > - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SI= ZE); > n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); > n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); > n->temperature =3D NVME_TEMPERATURE; > @@ -6498,7 +6495,10 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev, Error **errp) > pcie_ari_init(pci_dev, 0x100, 1); > } > =20 > - bar_size =3D QEMU_ALIGN_UP(n->reg_size, 4 * KiB); > + /* add one to max_ioqpairs to account for the admin queue pair */ > + bar_size =3D sizeof(NvmeBar) + > + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE; > + bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); > msix_table_offset =3D bar_size; > msix_table_size =3D PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize; > =20 > @@ -6512,7 +6512,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev, Error **errp) > =20 > memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); > memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme= ", > - n->reg_size); > + msix_table_offset); > memory_region_add_subregion(&n->bar0, 0, &n->iomem); > =20 > if (pci_is_vf(pci_dev)) { > diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h > index 927890b490..1401ac3904 100644 > --- a/hw/nvme/nvme.h > +++ b/hw/nvme/nvme.h > @@ -414,7 +414,6 @@ typedef struct NvmeCtrl { > uint16_t max_prp_ents; > uint16_t cqe_size; > uint16_t sqe_size; > - uint32_t reg_size; > uint32_t max_q_ents; > uint8_t outstanding_aers; > uint32_t irq_status; > --=20 > 2.25.1 >=20 Nice catch. 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