From: David Gibson <david@gibson.dropbear.id.au>
To: Fabiano Rosas <farosas@linux.ibm.com>
Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org, clg@kaod.org
Subject: Re: [PATCH 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
Date: Wed, 16 Feb 2022 13:16:55 +1100 [thread overview]
Message-ID: <Ygxel7VLY5sunzBY@yekko> (raw)
In-Reply-To: <20220215214148.1848266-10-farosas@linux.ibm.com>
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On Tue, Feb 15, 2022 at 06:41:30PM -0300, Fabiano Rosas wrote:
> We're considering these two to be from different CPU families, so
> duplicate some code to keep them separate.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/cpu_init.c | 107 +++++++++++++++++++++++++++++++++++-------
> 1 file changed, 91 insertions(+), 16 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 6a367f2bbc..79cd14d49c 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -803,6 +803,97 @@ static void register_G2_sprs(CPUPPCState *env)
>
> static void register_74xx_sprs(CPUPPCState *env)
> {
> + /* Breakpoints */
> + spr_register_kvm(env, SPR_DABR, "DABR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_DABR, 0x00000000);
> +
> + spr_register(env, SPR_IABR, "IABR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* Cache management */
> + spr_register(env, SPR_ICTC, "ICTC",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + /* Performance monitors */
> + spr_register(env, SPR_7XX_MMCR0, "MMCR0",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_MMCR1, "MMCR1",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_PMC1, "PMC1",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_PMC2, "PMC2",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_PMC3, "PMC3",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_PMC4, "PMC4",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_SIAR, "SIAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_UPMC1, "UPMC1",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_UPMC2, "UPMC2",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_UPMC3, "UPMC3",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_UPMC4, "UPMC4",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +
> + spr_register(env, SPR_7XX_USIAR, "USIAR",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + /* External access control */
> + spr_register(env, SPR_EAR, "EAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +
> /* Processor identification */
> spr_register(env, SPR_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4644,8 +4735,6 @@ static void init_proc_7400(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
>
> @@ -4718,8 +4807,6 @@ static void init_proc_7410(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
>
> @@ -4799,8 +4886,6 @@ static void init_proc_7440(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
>
> @@ -4901,8 +4986,6 @@ static void init_proc_7450(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> @@ -5025,8 +5108,6 @@ static void init_proc_7445(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* LDSTCR */
> @@ -5156,8 +5237,6 @@ static void init_proc_7455(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> @@ -5289,8 +5368,6 @@ static void init_proc_7457(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> @@ -5442,8 +5519,6 @@ static void init_proc_e600(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> - register_7xx_sprs(env);
> - /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2022-02-16 5:14 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-15 21:41 [PATCH 00/27] target/ppc: SPR registration cleanups Fabiano Rosas
2022-02-15 21:41 ` [PATCH 01/27] target/ppc: cpu_init: Remove not implemented comments Fabiano Rosas
2022-02-16 2:05 ` David Gibson
2022-02-15 21:41 ` [PATCH 02/27] target/ppc: cpu_init: Remove G2LE init code Fabiano Rosas
2022-02-16 2:07 ` David Gibson
2022-02-15 21:41 ` [PATCH 03/27] target/ppc: cpu_init: Group registration of generic SPRs Fabiano Rosas
2022-02-16 2:10 ` David Gibson
2022-02-15 21:41 ` [PATCH 04/27] target/ppc: cpu_init: Move Timebase registration into the common function Fabiano Rosas
2022-02-16 2:11 ` David Gibson
2022-02-15 21:41 ` [PATCH 05/27] target/ppc: cpu_init: Avoid nested SPR register functions Fabiano Rosas
2022-02-16 2:12 ` David Gibson
2022-02-15 21:41 ` [PATCH 06/27] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs Fabiano Rosas
2022-02-16 2:13 ` David Gibson
2022-02-15 21:41 ` [PATCH 07/27] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs Fabiano Rosas
2022-02-16 2:14 ` David Gibson
2022-02-15 21:41 ` [PATCH 08/27] target/ppc: cpu_init: Decouple G2 SPR registration from 755 Fabiano Rosas
2022-02-16 2:15 ` David Gibson
2022-02-15 21:41 ` [PATCH 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx Fabiano Rosas
2022-02-16 2:16 ` David Gibson [this message]
2022-02-15 21:41 ` [PATCH 10/27] target/ppc: cpu_init: Deduplicate 440 SPR registration Fabiano Rosas
2022-02-16 2:18 ` David Gibson
2022-02-15 21:41 ` [PATCH 11/27] target/ppc: cpu_init: Deduplicate 603 " Fabiano Rosas
2022-02-16 2:19 ` David Gibson
2022-02-15 21:41 ` [PATCH 12/27] target/ppc: cpu_init: Deduplicate 604 " Fabiano Rosas
2022-02-16 2:19 ` David Gibson
2022-02-15 21:41 ` [PATCH 13/27] target/ppc: cpu_init: Deduplicate 7xx " Fabiano Rosas
2022-02-16 2:23 ` David Gibson
2022-02-15 21:41 ` [PATCH 14/27] target/ppc: cpu_init: Deduplicate 755 " Fabiano Rosas
2022-02-16 2:23 ` David Gibson
2022-02-15 21:41 ` [PATCH 15/27] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function Fabiano Rosas
2022-02-16 2:24 ` David Gibson
2022-02-16 2:52 ` David Gibson
2022-02-15 21:41 ` [PATCH 16/27] target/ppc: cpu_init: Move e300 SPR registration " Fabiano Rosas
2022-02-16 2:26 ` David Gibson
2022-02-15 21:41 ` [PATCH 17/27] target/ppc: cpu_init: Move 604e " Fabiano Rosas
2022-02-16 2:50 ` David Gibson
2022-02-15 21:41 ` [PATCH 18/27] target/ppc: cpu_init: Reuse init_proc_603 for the e300 Fabiano Rosas
2022-02-16 2:27 ` David Gibson
2022-02-15 21:41 ` [PATCH 19/27] target/ppc: cpu_init: Reuse init_proc_604 for the 604e Fabiano Rosas
2022-02-16 2:50 ` David Gibson
2022-02-15 21:41 ` [PATCH 20/27] target/ppc: cpu_init: Reuse init_proc_745 for the 755 Fabiano Rosas
2022-02-16 2:54 ` David Gibson
2022-02-15 21:41 ` [PATCH 21/27] target/ppc: cpu_init: Rename software TLB function Fabiano Rosas
2022-02-16 2:56 ` David Gibson
2022-02-15 21:41 ` [PATCH 22/27] target/ppc: cpu_init: Rename register_ne_601_sprs Fabiano Rosas
2022-02-16 2:59 ` David Gibson
2022-02-16 13:19 ` Fabiano Rosas
2022-02-16 23:41 ` David Gibson
2022-02-15 21:41 ` [PATCH 23/27] target/ppc: cpu_init: Remove register_usprg3_sprs Fabiano Rosas
2022-02-16 2:59 ` David Gibson
2022-02-15 21:41 ` [PATCH 24/27] target/ppc: cpu_init: Expose some SPR registration helpers Fabiano Rosas
2022-02-16 3:00 ` David Gibson
2022-02-15 21:41 ` [PATCH 25/27] target/ppc: cpu_init: Move SPR registration macros to a header Fabiano Rosas
2022-02-16 3:01 ` David Gibson
2022-02-15 21:41 ` [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM " Fabiano Rosas
2022-02-16 3:04 ` David Gibson
2022-02-16 13:06 ` Fabiano Rosas
2022-02-16 23:32 ` David Gibson
2022-02-15 21:41 ` [PATCH 27/27] target/ppc: Move common SPR functions out of cpu_init Fabiano Rosas
2022-02-16 3:05 ` David Gibson
2022-02-16 3:06 ` [PATCH 00/27] target/ppc: SPR registration cleanups David Gibson
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