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Donenfeld" Cc: QEMU Developers , openrisc@lists.librecores.org, richard.henderson@linaro.org Subject: Re: [PATCH v2] hw/openrisc: use right OMPIC size variable Message-ID: References: <20220502232800.259036-1-Jason@zx2c4.com> <20220503094533.402157-1-Jason@zx2c4.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=shorne@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, May 04, 2022 at 01:10:04PM +0200, Jason A. Donenfeld wrote: > On Tue, May 3, 2022 at 10:22 PM Stafford Horne wrote: > > > > On Tue, May 03, 2022 at 11:45:33AM +0200, Jason A. Donenfeld wrote: > > > This appears to be a copy and paste error. The UART size was used > > > instead of the much smaller OMPIC size. But actually that smaller OMPIC > > > size is wrong too and doesn't allow the IPI to work in Linux. So set it > > > to the old value. > > > > > > Signed-off-by: Jason A. Donenfeld > > > --- > > > hw/openrisc/openrisc_sim.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c > > > index 99b14940f4..3218db6656 100644 > > > --- a/hw/openrisc/openrisc_sim.c > > > +++ b/hw/openrisc/openrisc_sim.c > > > @@ -78,7 +78,7 @@ static const struct MemmapEntry { > > > [OR1KSIM_DRAM] = { 0x00000000, 0 }, > > > [OR1KSIM_UART] = { 0x90000000, 0x100 }, > > > [OR1KSIM_ETHOC] = { 0x92000000, 0x800 }, > > > - [OR1KSIM_OMPIC] = { 0x98000000, 16 }, > > > + [OR1KSIM_OMPIC] = { 0x98000000, 0x100 }, > > > > Right, I missed this as part of my series. OMPIC will allocate 2 32-bit > > registers per CPU. I documented this here: > > > > - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-ompic.c > > > > I think what we will want here is something like: > > > > [OR1KSIM_OMPIC] = { 0x98000000, 8 * OR1KSIM_CPUS_MAX }, > > Do you want a v3 or are you going to fix it up yourself? I'll fix it up. -Stafford