* [PATCH 0/2] hw/nvme: support smart AEN
@ 2022-05-07 7:26 zhenwei pi
2022-05-07 7:26 ` [PATCH 1/2] hw/nvme: introduce smart bits of aen cfg zhenwei pi
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: zhenwei pi @ 2022-05-07 7:26 UTC (permalink / raw)
To: kbusch, its, k.jensen; +Cc: qemu-devel, qemu-block, hch, zhenwei pi
Hi,
In this series, firstly introduce smart related bits of aen cfg, then
support this in oaes.
Linux guest does not support this currently, I also send a series to
enable smart AEN:
https://lore.kernel.org/lkml/20220507065026.260306-1-pizhenwei@bytedance.com/T/#t
Test the two series together, works fine.
Zhenwei Pi (2):
hw/nvme: introduce smart bits of aen cfg
hw/nvme: support smart AEN
hw/nvme/ctrl.c | 9 ++++++++-
include/block/nvme.h | 8 +++++++-
2 files changed, 15 insertions(+), 2 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] hw/nvme: introduce smart bits of aen cfg
2022-05-07 7:26 [PATCH 0/2] hw/nvme: support smart AEN zhenwei pi
@ 2022-05-07 7:26 ` zhenwei pi
2022-05-07 7:26 ` [PATCH 2/2] hw/nvme: support smart AEN zhenwei pi
2022-05-09 11:12 ` [PATCH 0/2] " Klaus Jensen
2 siblings, 0 replies; 5+ messages in thread
From: zhenwei pi @ 2022-05-07 7:26 UTC (permalink / raw)
To: kbusch, its, k.jensen; +Cc: qemu-devel, qemu-block, hch, zhenwei pi
According to NVM Express v1.4, Section 5.21.1.11 (Asynchronous Event
Configuration), introduce bit 0 ~ bit 5.
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
---
include/block/nvme.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 3737351cc8..d92912f9ad 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -1122,7 +1122,13 @@ typedef struct NvmeIdCtrlNvm {
} NvmeIdCtrlNvm;
enum NvmeIdCtrlOaes {
- NVME_OAES_NS_ATTR = 1 << 8,
+ NVME_OAES_SMART_SPARE = NVME_SMART_SPARE,
+ NVME_OAES_SMART_TEMPERATURE = NVME_SMART_TEMPERATURE,
+ NVME_OAES_SMART_RELIABILITY = NVME_SMART_RELIABILITY,
+ NVME_OAES_SMART_MEDIA_READ_ONLY = NVME_SMART_MEDIA_READ_ONLY,
+ NVME_OAES_SMART_FAILED_VOLATILE_MEDIA = NVME_SMART_FAILED_VOLATILE_MEDIA,
+ NVME_OAES_SMART_PMR_UNRELIABLE = NVME_SMART_PMR_UNRELIABLE,
+ NVME_OAES_NS_ATTR = 1 << 8,
};
enum NvmeIdCtrlCtratt {
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] hw/nvme: support smart AEN
2022-05-07 7:26 [PATCH 0/2] hw/nvme: support smart AEN zhenwei pi
2022-05-07 7:26 ` [PATCH 1/2] hw/nvme: introduce smart bits of aen cfg zhenwei pi
@ 2022-05-07 7:26 ` zhenwei pi
2022-05-09 11:12 ` [PATCH 0/2] " Klaus Jensen
2 siblings, 0 replies; 5+ messages in thread
From: zhenwei pi @ 2022-05-07 7:26 UTC (permalink / raw)
To: kbusch, its, k.jensen; +Cc: qemu-devel, qemu-block, hch, zhenwei pi
Support smart AEN on controller side, if the guest side enables this
feature, after injecting smart critical warning, also raise AER.
This can be tested by:
virsh qemu-monitor-command vm '{ "execute": "qom-set", "arguments":
{ "path": "/machine/peripheral/nvme0",
"property": "smart_critical_warning", "value":1 } }'
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
---
hw/nvme/ctrl.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 03760ddeae..8236a746c8 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -6707,6 +6707,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
NvmeIdCtrl *id = &n->id_ctrl;
uint8_t *pci_conf = pci_dev->config;
uint64_t cap = ldq_le_p(&n->bar.cap);
+ uint32_t supported_oaes;
id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
@@ -6716,7 +6717,13 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->cntlid = cpu_to_le16(n->cntlid);
- id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR);
+ supported_oaes = NVME_OAES_SMART_SPARE | NVME_OAES_SMART_TEMPERATURE |
+ NVME_OAES_SMART_RELIABILITY |
+ NVME_OAES_SMART_MEDIA_READ_ONLY |
+ NVME_OAES_SMART_FAILED_VOLATILE_MEDIA |
+ NVME_OAES_SMART_PMR_UNRELIABLE |
+ NVME_OAES_NS_ATTR;
+ id->oaes = cpu_to_le32(supported_oaes);
id->ctratt |= cpu_to_le32(NVME_CTRATT_ELBAS);
id->rab = 6;
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] hw/nvme: support smart AEN
2022-05-07 7:26 [PATCH 0/2] hw/nvme: support smart AEN zhenwei pi
2022-05-07 7:26 ` [PATCH 1/2] hw/nvme: introduce smart bits of aen cfg zhenwei pi
2022-05-07 7:26 ` [PATCH 2/2] hw/nvme: support smart AEN zhenwei pi
@ 2022-05-09 11:12 ` Klaus Jensen
2022-05-09 12:36 ` zhenwei pi
2 siblings, 1 reply; 5+ messages in thread
From: Klaus Jensen @ 2022-05-09 11:12 UTC (permalink / raw)
To: zhenwei pi; +Cc: kbusch, k.jensen, qemu-devel, qemu-block, hch
[-- Attachment #1: Type: text/plain, Size: 928 bytes --]
On May 7 15:26, zhenwei pi wrote:
> Hi,
> In this series, firstly introduce smart related bits of aen cfg, then
> support this in oaes.
>
> Linux guest does not support this currently, I also send a series to
> enable smart AEN:
> https://lore.kernel.org/lkml/20220507065026.260306-1-pizhenwei@bytedance.com/T/#t
>
> Test the two series together, works fine.
>
> Zhenwei Pi (2):
> hw/nvme: introduce smart bits of aen cfg
> hw/nvme: support smart AEN
>
> hw/nvme/ctrl.c | 9 ++++++++-
> include/block/nvme.h | 8 +++++++-
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
I'm not quite sure what you are trying to achieve here. Bits 0 through 7
are reserved in OAES, they are not optional.
We already simply accept whatever the host configured with the
Asynchronous Event Configuration feature. And you added the support for
triggering custom AENs for those through the monitor.
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Re: [PATCH 0/2] hw/nvme: support smart AEN
2022-05-09 11:12 ` [PATCH 0/2] " Klaus Jensen
@ 2022-05-09 12:36 ` zhenwei pi
0 siblings, 0 replies; 5+ messages in thread
From: zhenwei pi @ 2022-05-09 12:36 UTC (permalink / raw)
To: Klaus Jensen; +Cc: kbusch, k.jensen, qemu-devel, qemu-block, hch
On 5/9/22 19:12, Klaus Jensen wrote:
> On May 7 15:26, zhenwei pi wrote:
>> Hi,
>> In this series, firstly introduce smart related bits of aen cfg, then
>> support this in oaes.
>>
>> Linux guest does not support this currently, I also send a series to
>> enable smart AEN:
>> https://lore.kernel.org/lkml/20220507065026.260306-1-pizhenwei@bytedance.com/T/#t
>>
>> Test the two series together, works fine.
>>
>> Zhenwei Pi (2):
>> hw/nvme: introduce smart bits of aen cfg
>> hw/nvme: support smart AEN
>>
>> hw/nvme/ctrl.c | 9 ++++++++-
>> include/block/nvme.h | 8 +++++++-
>> 2 files changed, 15 insertions(+), 2 deletions(-)
>>
>
> I'm not quite sure what you are trying to achieve here. Bits 0 through 7
> are reserved in OAES, they are not optional.
>
> We already simply accept whatever the host configured with the
> Asynchronous Event Configuration feature. And you added the support for
> triggering custom AENs for those through the monitor.
Oh, sorry, I misunderstand OAES[7:0]. Thanks for pointing this out!
--
zhenwei pi
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-05-09 12:49 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2022-05-07 7:26 [PATCH 0/2] hw/nvme: support smart AEN zhenwei pi
2022-05-07 7:26 ` [PATCH 1/2] hw/nvme: introduce smart bits of aen cfg zhenwei pi
2022-05-07 7:26 ` [PATCH 2/2] hw/nvme: support smart AEN zhenwei pi
2022-05-09 11:12 ` [PATCH 0/2] " Klaus Jensen
2022-05-09 12:36 ` zhenwei pi
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