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[35.230.65.123]) by smtp.gmail.com with ESMTPSA id t3-20020a6549c3000000b00411acdb1625sm8343810pgs.92.2022.07.18.13.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 13:13:02 -0700 (PDT) Date: Mon, 18 Jul 2022 20:12:58 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Zhenzhong Duan , qemu-devel@nongnu.org, mtosatti@redhat.com, likexu@tencent.com, xiangfeix.ma@intel.com Subject: Re: [PATCH] i386: Disable BTS and PEBS Message-ID: References: <20220718032206.34488-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=seanjc@google.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jul 18, 2022, Paolo Bonzini wrote: > This needs to be fixed in the kernel because old QEMU/new KVM is supported. I can't object to adding a quirk for this since KVM is breaking userspace, but on the KVM side we really need to stop "sanitizing" userspace inputs unless it puts the host at risk, because inevitably it leads to needing a quirk. > But apart from that, where does Linux check MSR_IA32_MISC_ENABLE_BTS_UNAVAIL > and MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL? The kernel uses synthetic feature flags that are set by: static void init_intel(struct cpuinfo_x86 *c) if (boot_cpu_has(X86_FEATURE_DS)) { unsigned int l1, l2; rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); if (!(l1 & (1<<11))) set_cpu_cap(c, X86_FEATURE_BTS); if (!(l1 & (1<<12))) set_cpu_cap(c, X86_FEATURE_PEBS); } and consumed by: void __init intel_ds_init(void) /* * No support for 32bit formats */ if (!boot_cpu_has(X86_FEATURE_DTES64)) return; x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;