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Fri, 29 Jul 2022 10:41:29 -0400 (EDT) Date: Fri, 29 Jul 2022 09:41:28 -0500 From: Patrick Williams To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: Iris Chen , peter@pjd.dev, pdel@fb.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, alistair@alistair23.me, kwolf@redhat.com, hreitz@redhat.com, peter.maydell@linaro.org, andrew@aj.id.au, joel@jms.id.au, thuth@redhat.com, lvivier@redhat.com, pbonzini@redhat.com, qemu-block@nongnu.org, dz4list@gmail.com Subject: Re: [RFC 0/3] Add Generic SPI GPIO model Message-ID: References: <20220728232322.2921703-1-irischenlj@fb.com> <435b3e89-f9fd-c257-b03d-a12d4b59ac6b@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0iO6xrwk87ZolTFE" Content-Disposition: inline In-Reply-To: <435b3e89-f9fd-c257-b03d-a12d4b59ac6b@kaod.org> Received-SPF: pass client-ip=66.111.4.26; envelope-from=patrick@stwcx.xyz; helo=out2-smtp.messagingengine.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=1.997, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0iO6xrwk87ZolTFE Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jul 29, 2022 at 03:25:55PM +0200, C=E9dric Le Goater wrote: > Hello Iris, >=20 > On 7/29/22 01:23, Iris Chen wrote: > > MOSI pin in spi_gpio: the mosi pin is not included and we poll the real= time value > > of the gpio for input bits to prevent bugs with caching the mosi value.= It was discovered > > during testing that when using the mosi pin as the input pin, the mosi = value was not > > being updated due to a kernel and aspeed_gpio model optimization.=20 >=20 > ah. We need help from Andrew ! the model should have a mosi pin . This discussion about SMC reminded me of something that might be leading to the issues we're seeing. Our hardware implementation uses the same GPIOs as one of the SMCs and doesn't use the SMC. It could be that both QEMU models (the SPI-GPIO and the SMC) are trying to grab the same GPIOs. --=20 Patrick Williams --0iO6xrwk87ZolTFE Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEBGD9ii4LE9cNbqJBqwNHzC0AwRkFAmLj8ZgACgkQqwNHzC0A wRkZvhAAgScFLj//BkHVTPNmqSHKmkJWkyxuN+0+1hESlu7L5S9ud+VncLTbDscT D+MrqHXBPNzca8qc2wSgGVkqBw7f+HyC59+L0GbiDcJIBbA+RsL4H3sw/9mR4tD4 1bEiuCAsPhSxfntoaIIsSHe9nbXcT38fakKcHQIHBkgKhcerSAbjwQl8nUgLBBYD LyfeEB00JdRD2t5CV6/SpuYo2xtTihp7Vl+SVzqRhJHuaznj+2eRy+967vTqSJVU P4jV31xOqilnJgWmlgAz5HEwR3GsVZ8RSWhCmnE7J5hui7M/eVAMQxGPjiQUSvE6 q7uMpDkYVq4rcirXhhImAoa7I2xP0WhxboJxxe+uvaX0vx5LOZ44JrVxqh+FT7wD 7oNu/egJbbwfbERmvaJsUU4hXRh6faVXTm9mjNQgHjeIGttCi/Jnvq8WBeR6fYI5 4iHf4Vw3EJNL/sT67fsA0gf8b0CzKCA37otbe9O8/nlKY0Gi6gwoD41lpa9HYm34 jVq/ZyXIgdJ2pduGFTSe8C6q2OfnGlqvjietM0tfIKprKgXd8ymjYwyr+XtODCnd rP3a99Z7EwM3zSQ4l0wL0Xxi81BoJe0BY1OkYUoJTG1vZuQPYft3VNsxoeGumikT UCzNNQiQMuIZI7VirbEQ8q6Fu3YT8IK/62TVEeg9b/oCYOan8tc= =M/ZB -----END PGP SIGNATURE----- --0iO6xrwk87ZolTFE--