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[70.31.27.79]) by smtp.gmail.com with ESMTPSA id g9-20020a05620a40c900b006bbe6e89bdcsm17567187qko.31.2022.10.05.06.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 06:53:58 -0700 (PDT) Date: Wed, 5 Oct 2022 09:53:57 -0400 From: Peter Xu To: "Dr. David Alan Gilbert" Cc: qemu-devel@nongnu.org, Manish Mishra , Juan Quintela , ani@anisinha.ca, Leonardo Bras Soares Passos , "Daniel P . Berrange" Subject: Re: [PATCH 06/14] migration: Use atomic ops properly for page accountings Message-ID: References: <20220920225106.48451-1-peterx@redhat.com> <20220920225212.48785-1-peterx@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Oct 05, 2022 at 12:38:05PM +0100, Dr. David Alan Gilbert wrote: > * Peter Xu (peterx@redhat.com) wrote: > > On Tue, Oct 04, 2022 at 05:59:36PM +0100, Dr. David Alan Gilbert wrote: > > > * Peter Xu (peterx@redhat.com) wrote: > > > > To prepare for thread-safety on page accountings, at least below counters > > > > need to be accessed only atomically, they are: > > > > > > > > ram_counters.transferred > > > > ram_counters.duplicate > > > > ram_counters.normal > > > > ram_counters.postcopy_bytes > > > > > > > > There are a lot of other counters but they won't be accessed outside > > > > migration thread, then they're still safe to be accessed without atomic > > > > ops. > > > > > > > > Signed-off-by: Peter Xu > > > > > > I think this is OK; I'm not sure whether the memset 0's of ram_counters > > > technically need changing. > > > > IMHO they're fine - what we need there should be thing like WRITE_ONCE() > > just to make sure no register caches (actually atomic_write() is normally > > implemented with WRITE_ONCE afaik). But I think that's already guaranteed > > by memset() as the function call does, so we should be 100% safe. > > I agree you're probably OK. > > > > I'd love to put a comment somewhere saying these fields need to be > > > atomically read, but their qapi defined so I don't think we can. > > > > How about I add a comment above ram_counters declarations in ram.c? > > Yeh. > > > > > > > Finally, we probably need to check these are happy on 32 bit builds, > > > sometimes it's a bit funny with atomic adds. > > > > Yeah.. I hope using qatomic_*() APIs can help me avoid any issues. Or > > anything concerning? I'd be happy to test on specific things if there are. > > I just remember hitting problems in the past; especially if we end up > with trying to do a 64 bit atomic on a platofmr that can only do 32??? I see what you meant... when I was looking in the existing callers of qatomic_add(), I do find that we seem to have Stat64 just for that !CONFIG_ATOMIC64 problem. I'll dig a bit on whether and how we can do that; the thing is these counters are in the qapi so I need to make sure it can support Stat64 somehow. Hmm.. -- Peter Xu