From: Stefan Hajnoczi <stefanha@redhat.com>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: qemu-devel@nongnu.org, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL v2 00/22] riscv-to-apply queue
Date: Tue, 27 Sep 2022 11:04:48 -0400 [thread overview]
Message-ID: <YzMREOqWwN2iFhDF@fedora> (raw)
In-Reply-To: <20220927063104.2846825-1-alistair.francis@opensource.wdc.com>
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.
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prev parent reply other threads:[~2022-09-27 15:38 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 6:30 [PULL v2 00/22] riscv-to-apply queue Alistair Francis
2022-09-27 6:30 ` [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-27 6:30 ` [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-27 6:30 ` [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-27 6:30 ` [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-27 6:30 ` [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-27 6:30 ` [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-27 6:30 ` [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-27 6:30 ` [PULL v2 08/22] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-27 6:30 ` [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-27 6:30 ` [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-27 6:30 ` [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-27 6:30 ` [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-27 6:30 ` [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type Alistair Francis
2022-09-27 6:30 ` [PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Alistair Francis
2022-09-27 6:30 ` [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Alistair Francis
2022-09-27 6:30 ` [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written Alistair Francis
2022-09-27 6:30 ` [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR Alistair Francis
2022-09-27 6:31 ` [PULL v2 18/22] target/riscv: debug: Create common trigger actions function Alistair Francis
2022-09-27 6:31 ` [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger Alistair Francis
2022-09-27 6:31 ` [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code Alistair Francis
2022-09-27 6:31 ` [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered Alistair Francis
2022-09-27 15:04 ` Stefan Hajnoczi [this message]
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