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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2025 19:16:29.7609 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 591efe52-edb7-423b-7e04-08dd6c9ab688 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5632 Received-SPF: permerror client-ip=2a01:111:f403:2417::62f; envelope-from=nicolinc@nvidia.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 26, 2025 at 02:38:04PM +0100, Eric Auger wrote: > > +/* Update batch->ncmds to the number of execute cmds */ > > +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch) > > +{ > > + SMMUv3AccelState *s_accel = ARM_SMMUV3_ACCEL(bs); > > + uint32_t total = batch->ncmds; > > + IOMMUFDViommu *viommu_core; > > + int ret; > > + > > + if (!bs->accel) { > > + return 0; > > + } > > + > > + if (!s_accel->viommu) { > > + return 0; > > + } > > + viommu_core = &s_accel->viommu->core; > > + ret = iommufd_backend_invalidate_cache(viommu_core->iommufd, > > + viommu_core->viommu_id, > > + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3, > > + sizeof(Cmd), &batch->ncmds, > > + batch->cmds); > > + if (total != batch->ncmds) { > > + error_report("%s failed: ret=%d, total=%d, done=%d", > > + __func__, ret, total, batch->ncmds); > some commands may have been executed (batch->ncmds !=0). Is the > batch_cmds array updated accordingly? In the kernel doc I don't see any > mention of that. The uAPI kdoc of ioctl(IOMMU_HWPT_INVALIDATE) mentions: * @entry_num: Input the number of cache invalidation requests in the array. * Output the number of requests successfully handled by kernel. > Do you need to report a cmd_error as we do for some > other cmds? Yes, we do. And we did (in this patch)? cons would be updated: + if (batch->ncmds && (dev_cache != batch->dev_cache)) { + ret = smmuv3_accel_issue_cmd_batch(bs, batch); + if (ret) { + *cons = batch->cons[batch->ncmds]; + return ret; + } + } > > + return ret; > > + } > > + > > + batch->ncmds = 0; > > + batch->dev_cache = false; > > + return ret; > > +} > > + > > +int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, > I was confused by the name. The helper adds a single Cmd to the batch, > right? so batch_cmd would better suited. Yea, it could be "smmuv3_accel_batch_cmd". > > + SMMUCommandBatch *batch, Cmd *cmd, > > + uint32_t *cons, bool dev_cache) > > +{ > > + int ret; > > + > > + if (!bs->accel) { > > + return 0; > > + } > > + > > + if (sdev) { > > + SMMUv3AccelDevice *accel_dev; > > + accel_dev = container_of(sdev, SMMUv3AccelDevice, sdev); > > + if (!accel_dev->s1_hwpt) { > can it happen? in the positive can you add some comment to describe in > which condition? I recall this is for device cache specifically (i.e. CGFI_CD[_ALL] and ATC_INV) that I had in smmuv3_cmdq_consume(). Perhaps it gets here because Shameer separated the accel code from the non-accel smmuv3 file. This condition is to check if the device is attached to an accel HWPT, particularly to exclude commands being issued for emulated devices. Surely, if a device isn't attached to an accel stage-1 HWPT any more, we probably shouldn't forward the commands to the kernel? Though I start to suspect that we might need a lock for accel_dev->s1_hwpt? > > +/** > > + * SMMUCommandBatch - batch of invalidation commands for smmuv3-accel > > + * @cmds: Pointer to list of commands > > + * @cons: Pointer to list of CONS corresponding to the commands > > + * @ncmds: Total ncmds in the batch > number of commands OK. > > + * @dev_cache: Issue to a device cache > indicate whether the invalidation command batch targets device cache? Maybe "invalidation command batch targeting device cache or TLB". Thanks Nicolin