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Tue, 10 Dec 2024 17:28:19 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 10 Dec 2024 17:28:19 -0800 Received: from Asurada-Nvidia (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4 via Frontend Transport; Tue, 10 Dec 2024 17:28:18 -0800 Date: Tue, 10 Dec 2024 17:28:17 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: , , Shameer Kolothum , , , , , , , , Subject: Re: [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding Message-ID: References: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com> <20241108125242.60136-6-shameerali.kolothum.thodi@huawei.com> <20241211004821.GM2347147@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20241211004821.GM2347147@nvidia.com> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|CH3PR12MB9217:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ccc427a-281c-4802-564b-08dd19831d9d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(82310400026)(1800799024)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2024 01:28:28.3801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ccc427a-281c-4802-564b-08dd19831d9d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9217 Received-SPF: softfail client-ip=2a01:111:f403:2409::624; envelope-from=nicolinc@nvidia.com; helo=NAM04-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.52, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Dec 10, 2024 at 08:48:21PM -0400, Jason Gunthorpe wrote: > On Tue, Dec 10, 2024 at 03:01:48PM -0800, Nicolin Chen wrote: > > > Yet, here we seem to be missing a pathway between VMM and kernel > > to agree on the MSI window decided by the kernel, as this patch > > does the hard coding for a [0x8000000, 0x8100000) range. > > I would ideally turn it around and provide that range information to > the kernel and totally ignore the SW_MSI reserved region once > userspace provides it. Hmm.. that sounds like a uAPI for vITS range..but yes.. > The SW_MSI range then becomes something just used "by default". > > Haven't thought about exactly which ioctl could do > this.. SET_OPTION(SW_MSI) on the idevice perhaps? > > It seems pretty simple to do? That looks like a good interface, given that we are already making sw_msi_list per ictx. So, VMM can GET_OPTION(SW_MSI) for msi_base to extract the info from kernel. Likely need a second call for its length? Since IOMMU_OPTION only supports one val64 input or output. > We will eventually need a way for userspace to disable SW_MSI entirely > anyhow. > > I have been going through the structures between QEMU's SMMU code > > and virt/virt-acpi-build code, yet having a hard time to figure > > out a way to forward the MSI window from the SMMU code to IORT, > > especially after this series changes the "smmu" instance creation > > from virt code to "-device" string. Any thought? > > You probably have to solve this eventually because when the kernel > supports a non-RMR path the IORT code will need to not create the RMR > too. > > Using RMR, or not, and the address to put the SW_MSI, is probably part > of the global machine configuration in qemu. Yes, either vITS or RMR range is in the global machine code. So, likely it's not ideal to go with HWPTs. Thanks! Nicolin