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[99.254.114.190]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b6f10661f1sm48812285a.8.2024.12.11.14.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 14:25:21 -0800 (PST) Date: Wed, 11 Dec 2024 17:25:18 -0500 From: Peter Xu To: Peter Maydell Cc: Tomoyuki HIROSE , qemu-devel@nongnu.org, Paolo Bonzini , David Hildenbrand , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [RFC PATCH 2/5] system/memory: support unaligned access Message-ID: References: <20241108032952.56692-1-tomoyuki.hirose@igel.co.jp> <20241108032952.56692-3-tomoyuki.hirose@igel.co.jp> <2de74447-00f7-4bcf-81f3-c8461ec19a67@igel.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.472, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Dec 11, 2024 at 09:56:21AM +0000, Peter Maydell wrote: > On Fri, 6 Dec 2024 at 16:43, Peter Xu wrote: > > I assume it's about xhci_cap_ops then. If you agree we can also mention > > xhci_cap_ops when dscribing it, so readers can easily reference the MR > > attributes from the code alongside with understanding the use case. > > > > Does it mean that it could also work if xhci_cap_ops.impl.min_access_size > > can be changed to 2 (together with additional xhci_cap_read/write support)? > > > > Note that I'm not saying it must do so even if it would work for xHCI, but > > if the memory API change is only for one device, then it can still be > > discussed about which option would be better on changing the device or the > > core. > > I think the memory system core has been broken in this area > for a long time -- it purports to support impls which only > do a subset of what the valid operations are, but it actually > does buggy and wrong things in some cases. So far > we have effectively worked around it by avoiding defining > MemoryRegionOps that try to use the buggy areas, but I > think it's much better to fix the code so it really does > what it's theoretically intended to do. Thanks, Peter. I assume it means there're a lot of devices that can use this model. Then it makes perfect sense to do it in memory core. Though I do have some confusion on why we needed impl.unaligned at all. I see that Tomoyuki raised similar question, even if not exactly the same one. I'll try to continue the discussion there. -- Peter Xu