From: Zhao Liu <zhao1.liu@intel.com>
To: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-DaudÃ" <philmd@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 1/2] memattrs: Get rid of bit fields
Date: Tue, 21 Jan 2025 20:15:25 +0800 [thread overview]
Message-ID: <Z4+P3eHXqcU4Dqdx@intel.com> (raw)
In-Reply-To: <99397e13-e74e-45e0-8f2a-6d045407bc81@eviden.com>
Hi CLEMENT,
> > It still raises the size to 8 bytes but saves spare space, like:
> >
> > typedef struct MemTxAttrs {
> > unsigned int secure:1;
> > unsigned int space:2;
> > unsigned int user:1;
> > unsigned int memory:1;
> > unsigned int requester_id:16;
> > unsigned int pid:8;
> > bool unspecified;
> > uint8_t _reserved1;
> > uint16_t _reserved2;
> > } MemTxAttrs;
>
> Don't you think this will be an issue as some devices will need to
> support more than 256 PID/PASID? The PCIe spec allows using up to 20 bits.
>
Maybe we can have the layout of MeymTxAttrs like this:
typedef struct MemTxAttrs {
unsigned int pid:20;
uint16_t requester_id:16;
uint8_t secure:1;
uint8_t space:2;
uint8_t user:1;
uint8_t memory:1;
bool unspecified;
} MemTxAttrs;
I think a finer granularity division could solve this issue. And
there're still some spare spaces :-).
Thanks,
Zhao
next prev parent reply other threads:[~2025-01-21 11:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250120074258.2204342-1-zhao1.liu@intel.com>
[not found] ` <20250120074258.2204342-2-zhao1.liu@intel.com>
[not found] ` <CAFEAcA_VAOU+p_BC5bpnk2GKa5piywjf+yhFTh=-3O7TGut+uA@mail.gmail.com>
2025-01-20 16:38 ` [PATCH 1/2] memattrs: Get rid of bit fields Zhao Liu
2025-01-20 16:53 ` CLEMENT MATHIEU--DRIF
2025-01-21 12:15 ` Zhao Liu [this message]
2025-01-20 17:41 ` Paolo Bonzini
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