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Tue, 18 Feb 2025 14:31:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IERayIta+pjM26JHg5KM4EygLRLgNeffmUstLl7z0yuabvHxGORBQ6TlzA7nbm+5FwcGjg1hg== X-Received: by 2002:ac8:5e0b:0:b0:471:89f6:838d with SMTP id d75a77b69052e-471dbcc0ea4mr249062781cf.2.1739917869934; Tue, 18 Feb 2025 14:31:09 -0800 (PST) Received: from x1.local ([2604:7a40:2041:2b00::1000]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47202b63216sm10877761cf.24.2025.02.18.14.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 14:31:08 -0800 (PST) Date: Tue, 18 Feb 2025 17:31:05 -0500 From: Peter Xu To: Eric Auger Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com Subject: Re: [PATCH v3 0/5] Fix vIOMMU reset order Message-ID: References: <20250218182737.76722-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250218182737.76722-1-eric.auger@redhat.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.423, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Feb 18, 2025 at 07:25:30PM +0100, Eric Auger wrote: > With current reset scheme, DMA capable devices are reset after > the vIOMMU which translate them. This holds for the different > IOMMUs and various DMA capable devices such as virtio devices > and VFIO ones. With virtio devices, spurious traces can be > observed at qemu level such as "virtio: zero sized buffers are > not allowed" while for VFIO devices, translation faults can be > observed at host level. > > Virtio devices use 3 phase reset and virtio-pci devices are reset > in the 'hold' phase. VFIO device reset are registered using > qemu_register_reset() and as a consequence they are also reset > on 'hold' phase. > > Note that the tree of QOM devices resets depth-first but it does > so while enforcing the 3 phases. First the tree is traversed doing > the 'enter' phase, then the 'hold' phase and eventually the 'exit' > phase. > > However the QOM hierarchy is not built so that vIOMMUs get reset > after the DMA capable devices (IOMMUs are using either legacy reset > scheme or hold phase). Changing the QOM hierarchy does not sound > trivial while forcing the vIOMMUs to be reset on 'exit' phase > sounds reasonable and much simpler. Obviously this relies on the > assumption that all DMA capable devices quiesce their DMA before > (ie. during 'enter' or hold' phase). > > This was tested with qmp system_reset and virsh reset. Reviewed-by: Peter Xu -- Peter Xu