From: Mostafa Saleh <smostafa@google.com>
To: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org, jean-philippe@linaro.org,
peter.maydell@linaro.org, qemu-arm@nongnu.org,
richard.henderson@linaro.org
Subject: Re: [RFC PATCH v2 10/11] hw/arm/smmuv3: Populate OAS based on CPU PARANGE
Date: Tue, 21 Mar 2023 13:06:02 +0000 [thread overview]
Message-ID: <ZBmruj7OME3Pfbh1@google.com> (raw)
In-Reply-To: <6e6810c3-c01a-5a2f-4fed-64c9391e22ba@redhat.com>
Hi Eric,
> > + * According to 6.3.6 SMMU_IDR5, OAS must match the system physical address
> > + * size.
> > + */
> > + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> > + uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
> is this working in accelerated mode?
I didn't try with accel, I will give it a try, but from what I see, that
ARM_CPU() is used to get the CPU in traget/arm/kvm.c which is used from
accel/kvm-all.c, so it seems this would work for accelerated mode.
> > +
> > /**
> > * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
> > * multi-level stream table
> > @@ -265,7 +272,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
> > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
> > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
> > s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
> > - s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
> > + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, oas);
> I am not sure you can change that easily. In case of migration this is
> going to change the behavior of the device, no?
I see IDR registers are not migrated. I guess we can add them in a
subsection and if they were not passed (old instances) we set OAS to
44.
Maybe this should be another change outside of this series.
Thanks,
Mostafa
next prev parent reply other threads:[~2023-03-21 13:06 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-26 22:06 [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 01/11] hw/arm/smmuv3: Add missing fields for IDR0 Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 02/11] hw/arm/smmuv3: Update translation config to hold stage-2 Mostafa Saleh
2023-03-17 11:37 ` Eric Auger
2023-03-17 14:43 ` Mostafa Saleh
2023-03-17 17:36 ` Eric Auger
2023-02-26 22:06 ` [RFC PATCH v2 03/11] hw/arm/smmuv3: Refactor stage-1 PTW Mostafa Saleh
2023-03-17 18:31 ` Eric Auger
2023-03-19 8:38 ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 04/11] hw/arm/smmuv3: Add page table walk for stage-2 Mostafa Saleh
2023-03-20 14:56 ` Eric Auger
2023-03-20 18:52 ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 05/11] hw/arm/smmuv3: Parse STE config " Mostafa Saleh
2023-03-20 15:14 ` Eric Auger
2023-03-20 19:11 ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 06/11] hw/arm/smmuv3: Make TLB lookup work " Mostafa Saleh
2023-03-20 16:05 ` Eric Auger
2023-03-20 19:14 ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 07/11] hw/arm/smmuv3: Add VMID to tlb tagging Mostafa Saleh
2023-03-20 16:16 ` Eric Auger
2023-02-26 22:06 ` [RFC PATCH v2 08/11] hw/arm/smmuv3: Add CMDs related to stage-2 Mostafa Saleh
2023-03-20 16:51 ` Eric Auger
2023-03-20 19:29 ` Mostafa Saleh
2023-02-26 22:06 ` [RFC PATCH v2 09/11] hw/arm/smmuv3: Add stage-2 support in iova notifier Mostafa Saleh
2023-03-20 16:57 ` Eric Auger
2023-02-26 22:06 ` [RFC PATCH v2 10/11] hw/arm/smmuv3: Populate OAS based on CPU PARANGE Mostafa Saleh
2023-03-20 17:12 ` Eric Auger
2023-03-21 13:06 ` Mostafa Saleh [this message]
2023-03-21 13:23 ` Eric Auger
2023-03-21 13:29 ` Mostafa Saleh
2023-03-21 13:34 ` Eric Auger
2023-03-21 13:34 ` Peter Maydell
2023-03-21 13:42 ` Mostafa Saleh
2023-03-21 13:45 ` Eric Auger
2023-03-21 13:54 ` Mostafa Saleh
2023-03-21 14:08 ` Peter Maydell
2023-02-26 22:06 ` [RFC PATCH v2 11/11] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Mostafa Saleh
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