* [RESEND PATCH v2] target/i386: Switch back XFRM value
@ 2022-10-26 11:57 Yang Zhong
2022-10-27 0:28 ` Yang, Weijiang
0 siblings, 1 reply; 5+ messages in thread
From: Yang Zhong @ 2022-10-26 11:57 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, weijiang.yang, yang.zhong, Yang Zhong
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ad623d91e4..19aaed877b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
} else {
*eax &= env->features[FEAT_SGX_12_1_EAX];
*ebx &= 0; /* ebx reserve */
- *ecx &= env->features[FEAT_XSAVE_XSS_LO];
- *edx &= env->features[FEAT_XSAVE_XSS_HI];
+ *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
+ *edx &= env->features[FEAT_XSAVE_XCR0_HI];
/* FP and SSE are always allowed regardless of XSAVE/XCR0. */
*ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [RESEND PATCH v2] target/i386: Switch back XFRM value 2022-10-26 11:57 [RESEND PATCH v2] target/i386: Switch back XFRM value Yang Zhong @ 2022-10-27 0:28 ` Yang, Weijiang 2023-03-27 7:33 ` Christian Ehrhardt 0 siblings, 1 reply; 5+ messages in thread From: Yang, Weijiang @ 2022-10-27 0:28 UTC (permalink / raw) To: Zhong, Yang Cc: pbonzini@redhat.com, yang.zhong@linux.intel.com, qemu-devel@nongnu.org On 10/26/2022 7:57 PM, Zhong, Yang wrote: > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made > SGX enclave only supported SSE and x87 feature(xfrm=0x3). > > Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features") > > Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com> > --- > target/i386/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index ad623d91e4..19aaed877b 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > } else { > *eax &= env->features[FEAT_SGX_12_1_EAX]; > *ebx &= 0; /* ebx reserve */ > - *ecx &= env->features[FEAT_XSAVE_XSS_LO]; > - *edx &= env->features[FEAT_XSAVE_XSS_HI]; > + *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; > + *edx &= env->features[FEAT_XSAVE_XCR0_HI]; Oops, that's my fault to replace with wrong definitions, thanks for the fix! Reviewed-by: Yang Weijiang <weijiang.yang@intel.com> > > /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ > *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH v2] target/i386: Switch back XFRM value 2022-10-27 0:28 ` Yang, Weijiang @ 2023-03-27 7:33 ` Christian Ehrhardt 2023-03-27 8:03 ` Yang, Weijiang 0 siblings, 1 reply; 5+ messages in thread From: Christian Ehrhardt @ 2023-03-27 7:33 UTC (permalink / raw) To: Yang, Weijiang Cc: Zhong, Yang, pbonzini@redhat.com, yang.zhong@linux.intel.com, qemu-devel@nongnu.org On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang <weijiang.yang@intel.com> wrote: > > > On 10/26/2022 7:57 PM, Zhong, Yang wrote: > > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with > > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made > > SGX enclave only supported SSE and x87 feature(xfrm=0x3). > > > > Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features") > > > > Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com> > > --- > > target/i386/cpu.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index ad623d91e4..19aaed877b 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > } else { > > *eax &= env->features[FEAT_SGX_12_1_EAX]; > > *ebx &= 0; /* ebx reserve */ > > - *ecx &= env->features[FEAT_XSAVE_XSS_LO]; > > - *edx &= env->features[FEAT_XSAVE_XSS_HI]; > > + *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; > > + *edx &= env->features[FEAT_XSAVE_XCR0_HI]; > > Oops, that's my fault to replace with wrong definitions, thanks for the fix! > > Reviewed-by: Yang Weijiang <weijiang.yang@intel.com> Hi, I do not have any background on this but stumbled over this and wondered, is there any particular reason why this wasn't applied yet? It seemed to fix a former mistake, was acked and then ... silence > > > > /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ > > *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; > -- Christian Ehrhardt Senior Staff Engineer, Ubuntu Server Canonical Ltd ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH v2] target/i386: Switch back XFRM value 2023-03-27 7:33 ` Christian Ehrhardt @ 2023-03-27 8:03 ` Yang, Weijiang 2023-04-06 5:32 ` Yang Zhong 0 siblings, 1 reply; 5+ messages in thread From: Yang, Weijiang @ 2023-03-27 8:03 UTC (permalink / raw) To: Christian Ehrhardt, pbonzini@redhat.com Cc: Zhong, Yang, yang.zhong@linux.intel.com, qemu-devel@nongnu.org On 3/27/2023 3:33 PM, Christian Ehrhardt wrote: > On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang <weijiang.yang@intel.com> wrote: >> >> On 10/26/2022 7:57 PM, Zhong, Yang wrote: >>> The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with >>> FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made >>> SGX enclave only supported SSE and x87 feature(xfrm=0x3). >>> >>> Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features") >>> >>> Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com> >>> --- >>> target/i386/cpu.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >>> index ad623d91e4..19aaed877b 100644 >>> --- a/target/i386/cpu.c >>> +++ b/target/i386/cpu.c >>> @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, >>> } else { >>> *eax &= env->features[FEAT_SGX_12_1_EAX]; >>> *ebx &= 0; /* ebx reserve */ >>> - *ecx &= env->features[FEAT_XSAVE_XSS_LO]; >>> - *edx &= env->features[FEAT_XSAVE_XSS_HI]; >>> + *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; >>> + *edx &= env->features[FEAT_XSAVE_XCR0_HI]; >> Oops, that's my fault to replace with wrong definitions, thanks for the fix! >> >> Reviewed-by: Yang Weijiang <weijiang.yang@intel.com> > Hi, > I do not have any background on this but stumbled over this and wondered, > is there any particular reason why this wasn't applied yet? > > It seemed to fix a former mistake, was acked and then ... silence Chris, thanks for the catch! I double checked this patch isn't in the latest 8.0.0-rc1 tree. Hi, Paolo, Could you help merge this fixup patch? Thanks! > >>> /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ >>> *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [RESEND PATCH v2] target/i386: Switch back XFRM value 2023-03-27 8:03 ` Yang, Weijiang @ 2023-04-06 5:32 ` Yang Zhong 0 siblings, 0 replies; 5+ messages in thread From: Yang Zhong @ 2023-04-06 5:32 UTC (permalink / raw) To: Yang, Weijiang, Christian Ehrhardt Cc: Christian Ehrhardt, pbonzini@redhat.com, Zhong, Yang, qemu-devel@nongnu.org On Mon, Mar 27, 2023 at 04:03:54PM +0800, Yang, Weijiang wrote: > > On 3/27/2023 3:33 PM, Christian Ehrhardt wrote: > > On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang <weijiang.yang@intel.com> wrote: > > > > > > On 10/26/2022 7:57 PM, Zhong, Yang wrote: > > > > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with > > > > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made > > > > SGX enclave only supported SSE and x87 feature(xfrm=0x3). > > > > > > > > Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features") > > > > > > > > Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com> > > > > --- > > > > target/i386/cpu.c | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > > > index ad623d91e4..19aaed877b 100644 > > > > --- a/target/i386/cpu.c > > > > +++ b/target/i386/cpu.c > > > > @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > > > } else { > > > > *eax &= env->features[FEAT_SGX_12_1_EAX]; > > > > *ebx &= 0; /* ebx reserve */ > > > > - *ecx &= env->features[FEAT_XSAVE_XSS_LO]; > > > > - *edx &= env->features[FEAT_XSAVE_XSS_HI]; > > > > + *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; > > > > + *edx &= env->features[FEAT_XSAVE_XCR0_HI]; > > > Oops, that's my fault to replace with wrong definitions, thanks for the fix! > > > > > > Reviewed-by: Yang Weijiang <weijiang.yang@intel.com> > > Hi, > > I do not have any background on this but stumbled over this and wondered, > > is there any particular reason why this wasn't applied yet? > > > > It seemed to fix a former mistake, was acked and then ... silence > > Chris, thanks for the catch! > > I double checked this patch isn't in the latest 8.0.0-rc1 tree. > > > Hi, Paolo, > > Could you help merge this fixup patch? Thanks! Hello all, Let me rebase this patch and resend it, thanks! Yang > > > > > > > /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ > > > > *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; > > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-04-06 5:33 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-10-26 11:57 [RESEND PATCH v2] target/i386: Switch back XFRM value Yang Zhong 2022-10-27 0:28 ` Yang, Weijiang 2023-03-27 7:33 ` Christian Ehrhardt 2023-03-27 8:03 ` Yang, Weijiang 2023-04-06 5:32 ` Yang Zhong
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