[PATCH 0/2] Remove CBAR from A55/A76 and add A78

[PATCH 0/2] Remove CBAR from A55/A76 and add A78

[Jisheng Zhang]

patch1 removes CBAR from A55 and A76
patch2 adds A78 CPU

Jisheng Zhang (2):
  target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76
  target/arm: Add Cortex-A78 CPU

 docs/system/arm/virt.rst |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 71 ++++++++++++++++++++++++++++++++++++++--
 3 files changed, 71 insertions(+), 2 deletions(-)

-- 
2.40.0

[PATCH 1/2] target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76

[Jisheng Zhang]

Cortex-A55 and Cortex-A76 doesn't have CBAR, so remove CBAR feature
from them.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 target/arm/cpu64.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0fb07cc7b6..85dc9d57ff 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -796,7 +796,6 @@ static void aarch64_a55_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
@@ -919,7 +918,6 @@ static void aarch64_a76_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
-- 
2.40.0

[PATCH 2/2] target/arm: Add Cortex-A78 CPU

[Jisheng Zhang]

Enable the Cortex-A78 for virt to use a CPU type on the virt
board that models a specific real hardware CPU, rather than
have to use the QEMU-specific "max" CPU type.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 69 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 1cab33f02e..98cb53d977 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -58,6 +58,7 @@ Supported guest CPU types:
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
 - ``cortex-a76`` (64-bit)
+- ``cortex-a78`` (64-bit)
 - ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
 - ``neoverse-n1`` (64-bit)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ac626b3bef..4e00b58bdb 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -212,6 +212,7 @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
+    ARM_CPU_TYPE_NAME("cortex-a78"),
     ARM_CPU_TYPE_NAME("a64fx"),
     ARM_CPU_TYPE_NAME("neoverse-n1"),
     ARM_CPU_TYPE_NAME("host"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 85dc9d57ff..144004b522 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -977,6 +977,74 @@ static void aarch64_a76_initfn(Object *obj)
     cpu->isar.reset_pmcr_el0 = 0x410b3000;
 }
 
+static void aarch64_a78_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a78";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x8444C004;
+    cpu->dcz_blocksize = 4;
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x414fd412;          /* r1p2 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+    /* From B2.105 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.23 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    /* From B5.1 AdvSIMD AArch64 register summary */
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+
+    /* From D5.1 AArch64 PMU register summary */
+    cpu->isar.reset_pmcr_el0 = 0x41213000;
+}
+
 static void aarch64_a64fx_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -1377,6 +1445,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a55",         .initfn = aarch64_a55_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
+    { .name = "cortex-a78",         .initfn = aarch64_a78_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
     { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
-- 
2.40.0

[PATCH 0/2] Remove CBAR from A55/A76 and add A78

[Jisheng Zhang]

patch1 removes CBAR from A55 and A76
patch2 adds A78 CPU

Jisheng Zhang (2):
  target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76
  target/arm: Add Cortex-A78 CPU

 docs/system/arm/virt.rst |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 71 ++++++++++++++++++++++++++++++++++++++--
 3 files changed, 71 insertions(+), 2 deletions(-)

-- 
2.40.0

Re: [PATCH 0/2] Remove CBAR from A55/A76 and add A78

[Jisheng Zhang]

On Sat, Apr 15, 2023 at 04:36:55PM +0800, Jisheng Zhang wrote:
> patch1 removes CBAR from A55 and A76
> patch2 adds A78 CPU

For various reasons, I'd like to recall these two patches.

> 
> Jisheng Zhang (2):
>   target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76
>   target/arm: Add Cortex-A78 CPU
> 
>  docs/system/arm/virt.rst |  1 +
>  hw/arm/virt.c            |  1 +
>  target/arm/cpu64.c       | 71 ++++++++++++++++++++++++++++++++++++++--
>  3 files changed, 71 insertions(+), 2 deletions(-)
> 
> -- 
> 2.40.0
> 
> 

Re: [PATCH 0/2] Remove CBAR from A55/A76 and add A78

[Jisheng Zhang]

On Sat, Apr 15, 2023 at 04:28:25PM +0800, Jisheng Zhang wrote:
> patch1 removes CBAR from A55 and A76
> patch2 adds A78 CPU

As in another email, for various reaons I want to recall these two patches.

> 
> Jisheng Zhang (2):
>   target/arm: Remove ARM_FEATURE_CBAR_RO from A55 and A76
>   target/arm: Add Cortex-A78 CPU
> 
>  docs/system/arm/virt.rst |  1 +
>  hw/arm/virt.c            |  1 +
>  target/arm/cpu64.c       | 71 ++++++++++++++++++++++++++++++++++++++--
>  3 files changed, 71 insertions(+), 2 deletions(-)
> 
> -- 
> 2.40.0
> 
> 

Re: [PATCH 2/2] target/arm: Add Cortex-A78 CPU

[Marcin Juszkiewicz]

W dniu 15.04.2023 o 10:28, Jisheng Zhang pisze:
> Enable the Cortex-A78 for virt to use a CPU type on the virt
> board that models a specific real hardware CPU, rather than
> have to use the QEMU-specific "max" CPU type.

You can use 'neoverse-n1' to have a specific real hardware CPU.