From: Stafford Horne <shorne@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Development <qemu-devel@nongnu.org>,
Linux OpenRISC <linux-openrisc@vger.kernel.org>
Subject: Re: [PATCH v2 1/3] target/openrisc: Allow fpcsr access in user mode
Date: Thu, 11 May 2023 15:25:48 +0100 [thread overview]
Message-ID: <ZFz67B+EehEOx6g7@antec> (raw)
In-Reply-To: <c7e792c1-8229-8b6c-8e6a-1eda14d77c03@linaro.org>
On Wed, May 10, 2023 at 05:13:03PM +0100, Richard Henderson wrote:
> On 5/10/23 16:32, Stafford Horne wrote:
> > void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
> > {
> > -#ifndef CONFIG_USER_ONLY
> > OpenRISCCPU *cpu = env_archcpu(env);
> > +#ifndef CONFIG_USER_ONLY
> > CPUState *cs = env_cpu(env);
>
> Pulled cpu out if ifdef here...
>
> > @@ -204,10 +220,22 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
> > OpenRISCCPU *cpu = env_archcpu(env);
> > CPUState *cs = env_cpu(env);
> > int idx;
> > +#else
> > + OpenRISCCPU *cpu = env_archcpu(env);
> > #endif
>
> But replicated it here.
Right, let me make it consistent in this patch.
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Thank you,
-Stafford
next prev parent reply other threads:[~2023-05-11 14:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-10 15:32 [PATCH v2 0/3] OpenRISC updates for user space FPU Stafford Horne
2023-05-10 15:32 ` [PATCH v2 1/3] target/openrisc: Allow fpcsr access in user mode Stafford Horne
2023-05-10 16:13 ` Richard Henderson
2023-05-11 14:25 ` Stafford Horne [this message]
2023-05-10 15:32 ` [PATCH v2 2/3] target/openrisc: Set PC to cpu state on FPU exception Stafford Horne
2023-05-10 16:13 ` Richard Henderson
2023-05-10 15:32 ` [PATCH v2 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Stafford Horne
2023-05-10 16:16 ` Richard Henderson
2023-05-11 14:33 ` Stafford Horne
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