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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id l11-20020a05600c1d0b00b003f1978bbcd6sm12077257wms.3.2023.05.11.07.33.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 07:33:04 -0700 (PDT) Date: Thu, 11 May 2023 15:33:04 +0100 From: Stafford Horne To: Richard Henderson Cc: QEMU Development , Linux OpenRISC Subject: Re: [PATCH v2 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Message-ID: References: <20230510153228.264954-1-shorne@gmail.com> <20230510153228.264954-4-shorne@gmail.com> <390d7ef2-1240-55a3-4b13-ab8796921b7a@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <390d7ef2-1240-55a3-4b13-ab8796921b7a@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=shorne@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, May 10, 2023 at 05:16:20PM +0100, Richard Henderson wrote: > On 5/10/23 16:32, Stafford Horne wrote: > > OpenRISC defines tininess to be detected before rounding. Setup qemu to > > obey this. > > > > Signed-off-by: Stafford Horne > > --- > > Since v1: > > - Remove setting default NaN behavior. I discussed with the FPU developers and > > they mentioned the OpenRISC hardware should be IEEE compliant when handling > > and forwarding NaN payloads, and they don't want try change this. > > There is no such thing as IEEE compliant for NaN payloads. > All of that is implementation defined. I see, I haven't yet seen to IEEE 754 spec so I don't know how much is covered. It was incorrect to assume forwarding semantics was covered. > All OpenRISC needs to do is document its intentions (and then double-check > that fpu/softfloat-specialize.c.inc does what is documented). Understood, that makes sense, also reading that code I see how all other architectures are able to ifdef their way to a specific behavior. I will see what our current implementions do and update the spec and qemu as a separate task. > > Anyway, back to this patch, > Reviewed-by: Richard Henderson > > :-) Thank you ^_^ -Stafford