[PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids

[PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids

[Tao Su]

This patch series mainly updates SapphireRapids CPU model and adds
new CPU model EmeraldRapids and GraniteRapids.

Bit 13 (ARCH_CAP_FBSDP_NO), bit 14 (ARCH_CAP_FBSDP_NO) and bit 15
(ARCH_CAP_PSDP_NO) of MSR_IA32_ARCH_CAPABILITIES are enumerated starting
from latest SapphireRapids, which are missed in current SapphireRapids
CPU model, so add a new version for SapphireRapids CPU model to expose
these bits.

Add EmeraldRapids CPU model to this series, since EmeraldRapids also
enumerates these bits. The original patch of EmeraldRapids CPU model is
in [1].

GraniteRapids is Intel's successor to EmeraldRapids, an Intel 3 process
microarchitecture for enthusiasts and servers, which adds new features
based on SapphireRapids and EmeraldRapids.

[1]
https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian.wen@intel.com/

Lei Wang (1):
  target/i386: Add few security fix bits in ARCH_CAPABILITIES into
    SapphireRapids CPU model

Qian Wen (1):
  target/i386: Add new CPU model EmeraldRapids

Tao Su (5):
  target/i386: Add FEAT_7_1_EDX to adjust feature level
  target/i386: Add support for MCDT_NO in CPUID enumeration
  target/i386: Allow MCDT_NO if host supports
  target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
  target/i386: Add new CPU model GraniteRapids

 target/i386/cpu.c     | 303 +++++++++++++++++++++++++++++++++++++++++-
 target/i386/cpu.h     |   8 ++
 target/i386/kvm/kvm.c |   5 +
 3 files changed, 314 insertions(+), 2 deletions(-)


base-commit: 7efd65423ab22e6f5890ca08ae40c84d6660242f
-- 
2.34.1

[PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level

[Tao Su]

Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
non-zero, guest may report wrong maximum number sub-leaves in leaf
07H. So add FEAT_7_1_EDX to adjust feature level.

Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
enumeration")

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
 target/i386/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1242bd541a..e8a70c35d2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6778,6 +6778,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
         x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
         x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
         x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
+        x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
-- 
2.34.1

Re: [PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level

[Igor Mammedov]

On Fri, 16 Jun 2023 11:23:05 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> non-zero,
Can you clarify when/why that happens?

> guest may report wrong maximum number sub-leaves in leaf
> 07H. So add FEAT_7_1_EDX to adjust feature level.
> 
> Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
> enumeration")
> 
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
>  target/i386/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 1242bd541a..e8a70c35d2 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -6778,6 +6778,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
>          x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
>          x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
>          x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
> +        x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
>          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
>          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
>          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);

Re: [PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level

[Tao Su]

On Mon, Jun 26, 2023 at 02:39:15PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:05 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
> 
> > Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> > non-zero,
> Can you clarify when/why that happens?

When start a VM on GraniteRapids using '-cpu host', we can see two leafs CPUID_7_0
and CPUID_7_1 in VM, because both CPUID_7_1_EAX and CPUID_7_1_EDX have non-zero value:
0x00000007 0x01: eax=0x00201c30 edx=0x00004000

But if we minus all FEAT_7_1_EAX features using
'-cpu host,-avx-vnni,-avx512-bf16,-fzrm,-fsrs,-fsrc,-amx-fp16', we can't get CPUID_7_1
leaf even though CPUID_7_1_EDX has non-zero value, so it is necessary to update
cpuid_level_func7 by CPUID_7_1_EDX.

Thanks,
Tao

> 
> > guest may report wrong maximum number sub-leaves in leaf
> > 07H. So add FEAT_7_1_EDX to adjust feature level.
> > 
> > Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
> > enumeration")
> > 
> > Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> > ---
> >  target/i386/cpu.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 1242bd541a..e8a70c35d2 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -6778,6 +6778,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
> >          x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
> >          x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
> >          x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
> > +        x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
> >          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
> >          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
> >          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
> 
> 

Re: [PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level

[Igor Mammedov]

On Tue, 27 Jun 2023 12:27:19 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> On Mon, Jun 26, 2023 at 02:39:15PM +0200, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:05 +0800
> > Tao Su <tao1.su@linux.intel.com> wrote:
> >   
> > > Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> > > non-zero,  
> > Can you clarify when/why that happens?  
> 
> When start a VM on GraniteRapids using '-cpu host', we can see two leafs CPUID_7_0
> and CPUID_7_1 in VM, because both CPUID_7_1_EAX and CPUID_7_1_EDX have non-zero value:
> 0x00000007 0x01: eax=0x00201c30 edx=0x00004000
> 
> But if we minus all FEAT_7_1_EAX features using
> '-cpu host,-avx-vnni,-avx512-bf16,-fzrm,-fsrs,-fsrc,-amx-fp16', we can't get CPUID_7_1
> leaf even though CPUID_7_1_EDX has non-zero value, so it is necessary to update
> cpuid_level_func7 by CPUID_7_1_EDX.

Pls, explain that in commit message.
 
> Thanks,
> Tao
> 
> >   
> > > guest may report wrong maximum number sub-leaves in leaf
> > > 07H. So add FEAT_7_1_EDX to adjust feature level.
> > > 
> > > Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
> > > enumeration")
> > > 
> > > Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> > > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> > > ---
> > >  target/i386/cpu.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > index 1242bd541a..e8a70c35d2 100644
> > > --- a/target/i386/cpu.c
> > > +++ b/target/i386/cpu.c
> > > @@ -6778,6 +6778,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
> > >          x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
> > >          x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
> > >          x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
> > > +        x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
> > >          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
> > >          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
> > >          x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);  
> > 
> >   
> 

[PATCH 2/7] target/i386: Add support for MCDT_NO in CPUID enumeration

[Tao Su]

CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate
this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT)
behavior and do not need to be mitigated to avoid data-dependent behavior
for certain instructions.

Since MCDT_NO is in a new sub-leaf, add a new CPUID feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
 target/i386/cpu.c | 26 ++++++++++++++++++++++++++
 target/i386/cpu.h |  4 ++++
 2 files changed, 30 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e8a70c35d2..7898a4c79a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -668,6 +668,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
           CPUID_7_1_EAX_FSRC)
 #define TCG_7_1_EDX_FEATURES 0
+#define TCG_7_2_EDX_FEATURES 0
 #define TCG_APM_FEATURES 0
 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
@@ -910,6 +911,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         },
         .tcg_features = TCG_7_1_EDX_FEATURES,
     },
+    [FEAT_7_2_EDX] = {
+        .type = CPUID_FEATURE_WORD,
+        .feat_names = {
+            NULL, NULL, NULL, NULL,
+            NULL, "mcdt-no", NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, NULL,
+        },
+        .cpuid = {
+            .eax = 7,
+            .needs_ecx = true, .ecx = 2,
+            .reg = R_EDX,
+        },
+        .tcg_features = TCG_7_2_EDX_FEATURES,
+    },
     [FEAT_8000_0007_EDX] = {
         .type = CPUID_FEATURE_WORD,
         .feat_names = {
@@ -5919,6 +5939,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
             *edx = env->features[FEAT_7_1_EDX];
             *ebx = 0;
             *ecx = 0;
+        } else if (count == 2) {
+            *edx = env->features[FEAT_7_2_EDX];
+            *eax = 0;
+            *ebx = 0;
+            *ecx = 0;
         } else {
             *eax = 0;
             *ebx = 0;
@@ -6779,6 +6804,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
         x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
         x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
         x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
+        x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index cd047e0410..64d50acf41 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -628,6 +628,7 @@ typedef enum FeatureWord {
     FEAT_XSAVE_XSS_LO,     /* CPUID[EAX=0xd,ECX=1].ECX */
     FEAT_XSAVE_XSS_HI,     /* CPUID[EAX=0xd,ECX=1].EDX */
     FEAT_7_1_EDX,       /* CPUID[EAX=7,ECX=1].EDX */
+    FEAT_7_2_EDX,       /* CPUID[EAX=7,ECX=2].EDX */
     FEATURE_WORDS,
 } FeatureWord;
 
@@ -932,6 +933,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 /* PREFETCHIT0/1 Instructions */
 #define CPUID_7_1_EDX_PREFETCHITI       (1U << 14)
 
+/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
+#define CPUID_7_2_EDX_MCDT_NO           (1U << 5)
+
 /* XFD Extend Feature Disabled */
 #define CPUID_D_1_EAX_XFD               (1U << 4)
 
-- 
2.34.1

[PATCH 3/7] target/i386: Allow MCDT_NO if host supports

[Tao Su]

MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
 target/i386/kvm/kvm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index de531842f6..4defd8b479 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -432,6 +432,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
         uint32_t eax;
         host_cpuid(7, 1, &eax, &unused, &unused, &unused);
         ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
+    } else if (function == 7 && index == 2 && reg == R_EDX) {
+        /* Not new instructions, just an optimization.  */
+        uint32_t edx;
+        host_cpuid(7, 2, &unused, &unused, &unused, &edx);
+        ret |= edx & CPUID_7_2_EDX_MCDT_NO;
     } else if (function == 0xd && index == 0 &&
                (reg == R_EAX || reg == R_EDX)) {
         /*
-- 
2.34.1

Re: [PATCH 3/7] target/i386: Allow MCDT_NO if host supports

[Igor Mammedov]

On Fri, 16 Jun 2023 11:23:07 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> MCDT_NO bit indicates HW contains the security fix and doesn't need to
> be mitigated to avoid data-dependent behaviour for certain instructions.
> It needs no hypervisor support. Treat it as supported regardless of what
> KVM reports.
> 
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
>  target/i386/kvm/kvm.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index de531842f6..4defd8b479 100644
> --- a/target/i386/kvm/kvm.c
> +++ b/target/i386/kvm/kvm.c
> @@ -432,6 +432,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
>          uint32_t eax;
>          host_cpuid(7, 1, &eax, &unused, &unused, &unused);
>          ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
> +    } else if (function == 7 && index == 2 && reg == R_EDX) {

> +        /* Not new instructions, just an optimization.  */
comment doesn't make much sense to me, just drop it or
describe what MCDT_NO is/mitigates.

> +        uint32_t edx;
> +        host_cpuid(7, 2, &unused, &unused, &unused, &edx);
> +        ret |= edx & CPUID_7_2_EDX_MCDT_NO;
>      } else if (function == 0xd && index == 0 &&
>                 (reg == R_EAX || reg == R_EDX)) {
>          /*

Re: [PATCH 3/7] target/i386: Allow MCDT_NO if host supports

[Tao Su]

On Mon, Jun 26, 2023 at 03:03:12PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:07 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
> 
> > MCDT_NO bit indicates HW contains the security fix and doesn't need to
> > be mitigated to avoid data-dependent behaviour for certain instructions.
> > It needs no hypervisor support. Treat it as supported regardless of what
> > KVM reports.
> > 
> > Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> > ---
> >  target/i386/kvm/kvm.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> > index de531842f6..4defd8b479 100644
> > --- a/target/i386/kvm/kvm.c
> > +++ b/target/i386/kvm/kvm.c
> > @@ -432,6 +432,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
> >          uint32_t eax;
> >          host_cpuid(7, 1, &eax, &unused, &unused, &unused);
> >          ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
> > +    } else if (function == 7 && index == 2 && reg == R_EDX) {
> 
> > +        /* Not new instructions, just an optimization.  */
> comment doesn't make much sense to me, just drop it or
> describe what MCDT_NO is/mitigates.

Ok, I will drop it in the next version, thanks!

> 
> > +        uint32_t edx;
> > +        host_cpuid(7, 2, &unused, &unused, &unused, &edx);
> > +        ret |= edx & CPUID_7_2_EDX_MCDT_NO;
> >      } else if (function == 0xd && index == 0 &&
> >                 (reg == R_EAX || reg == R_EDX)) {
> >          /*
> 
> 

[PATCH 4/7] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES

[Tao Su]

Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions
and feature names.

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 target/i386/cpu.c | 4 ++--
 target/i386/cpu.h | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7898a4c79a..b5321240c6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1069,10 +1069,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
             "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
             "taa-no", NULL, NULL, NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
             NULL, "fb-clear", NULL, NULL,
             NULL, NULL, NULL, NULL,
-            NULL, NULL, NULL, NULL,
+            "pbrsb-no", NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
         },
         .msr = {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 64d50acf41..6221b1c0a4 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1022,7 +1022,11 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 #define MSR_ARCH_CAP_PSCHANGE_MC_NO     (1U << 6)
 #define MSR_ARCH_CAP_TSX_CTRL_MSR       (1U << 7)
 #define MSR_ARCH_CAP_TAA_NO             (1U << 8)
+#define MSR_ARCH_CAP_SBDR_SSDP_NO       (1u << 13)
+#define MSR_ARCH_CAP_FBSDP_NO           (1u << 14)
+#define MSR_ARCH_CAP_PSDP_NO            (1u << 15)
 #define MSR_ARCH_CAP_FB_CLEAR           (1U << 17)
+#define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
 
 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
 
-- 
2.34.1

Re: [PATCH 4/7] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES

[Igor Mammedov]

On Fri, 16 Jun 2023 11:23:08 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
> disclosed for fixing security issues, so add those bit definitions
> and feature names.
> 
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

> ---
>  target/i386/cpu.c | 4 ++--
>  target/i386/cpu.h | 4 ++++
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 7898a4c79a..b5321240c6 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1069,10 +1069,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>              "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
>              "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
>              "taa-no", NULL, NULL, NULL,
> -            NULL, NULL, NULL, NULL,
> +            NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
>              NULL, "fb-clear", NULL, NULL,
>              NULL, NULL, NULL, NULL,
> -            NULL, NULL, NULL, NULL,
> +            "pbrsb-no", NULL, NULL, NULL,
>              NULL, NULL, NULL, NULL,
>          },
>          .msr = {
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 64d50acf41..6221b1c0a4 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1022,7 +1022,11 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
>  #define MSR_ARCH_CAP_PSCHANGE_MC_NO     (1U << 6)
>  #define MSR_ARCH_CAP_TSX_CTRL_MSR       (1U << 7)
>  #define MSR_ARCH_CAP_TAA_NO             (1U << 8)
> +#define MSR_ARCH_CAP_SBDR_SSDP_NO       (1u << 13)
> +#define MSR_ARCH_CAP_FBSDP_NO           (1u << 14)
> +#define MSR_ARCH_CAP_PSDP_NO            (1u << 15)
>  #define MSR_ARCH_CAP_FB_CLEAR           (1U << 17)
> +#define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
>  
>  #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
>  

[PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

[Tao Su]

From: Lei Wang <lei4.wang@intel.com>

Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
fixes.

Add version 2 of SapphireRapids CPU model with those bits enabled also.

Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
 target/i386/cpu.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5321240c6..f84fd20bb1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "Intel Xeon Processor (SapphireRapids)",
         .versions = (X86CPUVersionDefinition[]) {
             { .version = 1 },
-            { /* end of list */ },
-        },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "sbdr-ssdp-no", "on" },
+                    { "fbsdp-no", "on" },
+                    { "psdp-no", "on" },
+                    { /* end of list */ }
+                }
+            },
+            { /* end of list */ }
+        }
     },
     {
         .name = "Denverton",
-- 
2.34.1

Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

[Igor Mammedov]

On Fri, 16 Jun 2023 11:23:09 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> From: Lei Wang <lei4.wang@intel.com>
> 
> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> fixes.
> 
> Add version 2 of SapphireRapids CPU model with those bits enabled also.

don't we need to update stepping value to 8 as well?

> 
> Signed-off-by: Lei Wang <lei4.wang@intel.com>
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> ---
>  target/i386/cpu.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index b5321240c6..f84fd20bb1 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>          .model_id = "Intel Xeon Processor (SapphireRapids)",
>          .versions = (X86CPUVersionDefinition[]) {
>              { .version = 1 },
> -            { /* end of list */ },
> -        },
> +            {
> +                .version = 2,
> +                .props = (PropValue[]) {
> +                    { "sbdr-ssdp-no", "on" },
> +                    { "fbsdp-no", "on" },
> +                    { "psdp-no", "on" },
> +                    { /* end of list */ }
> +                }
> +            },
> +            { /* end of list */ }
> +        }
>      },
>      {
>          .name = "Denverton",

Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

[Xiaoyao Li]

On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:09 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
> 
>> From: Lei Wang <lei4.wang@intel.com>
>>
>> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
>> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
>> fixes.
>>
>> Add version 2 of SapphireRapids CPU model with those bits enabled also.
> 
> don't we need to update stepping value to 8 as well?

No need.

The commit message is misleading. There 3 bits and some other bits in 
MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they 
are enumerated with newer microcode.

>>
>> Signed-off-by: Lei Wang <lei4.wang@intel.com>
>> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
>> ---
>>   target/i386/cpu.c | 13 +++++++++++--
>>   1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index b5321240c6..f84fd20bb1 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>>           .model_id = "Intel Xeon Processor (SapphireRapids)",
>>           .versions = (X86CPUVersionDefinition[]) {
>>               { .version = 1 },
>> -            { /* end of list */ },
>> -        },
>> +            {
>> +                .version = 2,
>> +                .props = (PropValue[]) {
>> +                    { "sbdr-ssdp-no", "on" },
>> +                    { "fbsdp-no", "on" },
>> +                    { "psdp-no", "on" },
>> +                    { /* end of list */ }
>> +                }
>> +            },
>> +            { /* end of list */ }
>> +        }
>>       },
>>       {
>>           .name = "Denverton",
> 

Re: [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

[Igor Mammedov]

On Tue, 27 Jun 2023 14:10:17 +0800
Xiaoyao Li <xiaoyao.li@intel.com> wrote:

> On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:09 +0800
> > Tao Su <tao1.su@linux.intel.com> wrote:
> >   
> >> From: Lei Wang <lei4.wang@intel.com>
> >>
> >> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> >> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> >> fixes.
> >>
> >> Add version 2 of SapphireRapids CPU model with those bits enabled also.  
> > 
> > don't we need to update stepping value to 8 as well?  
> 
> No need.
> 
> The commit message is misleading. There 3 bits and some other bits in 
> MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they 
> are enumerated with newer microcode.

It that case fix commit message please.

> 
> >>
> >> Signed-off-by: Lei Wang <lei4.wang@intel.com>
> >> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> >> ---
> >>   target/i386/cpu.c | 13 +++++++++++--
> >>   1 file changed, 11 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index b5321240c6..f84fd20bb1 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> >>           .model_id = "Intel Xeon Processor (SapphireRapids)",
> >>           .versions = (X86CPUVersionDefinition[]) {
> >>               { .version = 1 },
> >> -            { /* end of list */ },
> >> -        },
> >> +            {
> >> +                .version = 2,
> >> +                .props = (PropValue[]) {
> >> +                    { "sbdr-ssdp-no", "on" },
> >> +                    { "fbsdp-no", "on" },
> >> +                    { "psdp-no", "on" },
> >> +                    { /* end of list */ }
> >> +                }
> >> +            },
> >> +            { /* end of list */ }
> >> +        }
> >>       },
> >>       {
> >>           .name = "Denverton",  
> >   
> 

[PATCH 6/7] target/i386: Add new CPU model EmeraldRapids

[Tao Su]

From: Qian Wen <qian.wen@intel.com>

Emerald Rapids (EMR) is the next generation of Xeon server processor
after Sapphire Rapids (SPR).

Currently, regarding the feature set that can be exposed to guest, there
isn't any one new comparing with SPR cpu model, except that EMR has a
different model number.

Though it's practicable to define EMR as an alias of a new version of
SPR by only updating the model number and model name, it loses the
flexibility when new version of EMR cpu model are needed for adding new
features (that hasn't virtalized/supported by KVM yet).

So just add EMR as a standalone cpu model.

Signed-off-by: Qian Wen <qian.wen@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
Changes to original patch
(https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian.wen@intel.com/)

- Add MSR_ARCH_CAP_SBDR_SSDP_NO, MSR_ARCH_CAP_FBSDP_NO and
  MSR_ARCH_CAP_PSDP_NO
---
 target/i386/cpu.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f84fd20bb1..7faf6dfaee 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3866,6 +3866,133 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             { /* end of list */ }
         }
     },
+    {
+        .name = "EmeraldRapids",
+        .level = 0x20,
+        .vendor = CPUID_VENDOR_INTEL,
+        .family = 6,
+        .model = 207,
+        .stepping = 1,
+        .features[FEAT_1_EDX] =
+            CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+            CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+            CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+            CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
+            CPUID_SSE | CPUID_SSE2,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
+            CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
+            CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+            CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
+            CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
+        .features[FEAT_8000_0008_EBX] =
+            CPUID_8000_0008_EBX_WBNOINVD,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
+            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
+            CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
+            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
+            CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
+            CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
+            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
+            CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
+            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
+            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
+            CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
+            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
+            CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
+            CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
+            CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
+            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
+            MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
+            MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
+            MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
+            MSR_ARCH_CAP_PSDP_NO,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .features[FEAT_7_1_EAX] =
+            CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
+            CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
+        .features[FEAT_VMX_BASIC] =
+            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+        .features[FEAT_VMX_ENTRY_CTLS] =
+            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+        .features[FEAT_VMX_EPT_VPID_CAPS] =
+            MSR_VMX_EPT_EXECONLY |
+            MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
+            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
+            MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+        .features[FEAT_VMX_EXIT_CTLS] =
+            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
+            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+        .features[FEAT_VMX_MISC] =
+            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+            MSR_VMX_MISC_VMWRITE_VMEXIT,
+        .features[FEAT_VMX_PINBASED_CTLS] =
+            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+            VMX_PIN_BASED_POSTED_INTR,
+        .features[FEAT_VMX_PROCBASED_CTLS] =
+            VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
+            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
+            VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
+            VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
+            VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
+            VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
+            VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
+            VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
+            VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
+            VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
+            VMX_CPU_BASED_PAUSE_EXITING |
+            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+        .features[FEAT_VMX_SECONDARY_CTLS] =
+            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+            VMX_SECONDARY_EXEC_RDTSCP |
+            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+            VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
+            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+            VMX_SECONDARY_EXEC_RDRAND_EXITING |
+            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+            VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+            VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
+            VMX_SECONDARY_EXEC_XSAVES,
+        .features[FEAT_VMX_VMFUNC] =
+            MSR_VMX_VMFUNC_EPT_SWITCHING,
+        .xlevel = 0x80000008,
+        .model_id = "Intel Xeon Processor (EmeraldRapids)",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            { /* end of list */ },
+        },
+    },
     {
         .name = "Denverton",
         .level = 21,
-- 
2.34.1

Re: [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids

[Igor Mammedov]

On Fri, 16 Jun 2023 11:23:10 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> From: Qian Wen <qian.wen@intel.com>
> 
> Emerald Rapids (EMR) is the next generation of Xeon server processor
> after Sapphire Rapids (SPR).
> 
> Currently, regarding the feature set that can be exposed to guest, there
> isn't any one new comparing with SPR cpu model, except that EMR has a
> different model number.
> 
> Though it's practicable to define EMR as an alias of a new version of
> SPR by only updating the model number and model name, it loses the
> flexibility when new version of EMR cpu model are needed for adding new
> features (that hasn't virtalized/supported by KVM yet).

Which begs a question, why do we need EMR model (or alias) at all
if it's the same as SPR at the moment.

Make new features supported 1st and only then introduce a new CPU model.

> 
> So just add EMR as a standalone cpu model.
> 
> Signed-off-by: Qian Wen <qian.wen@intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> ---
> Changes to original patch
> (https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian.wen@intel.com/)
> 
> - Add MSR_ARCH_CAP_SBDR_SSDP_NO, MSR_ARCH_CAP_FBSDP_NO and
>   MSR_ARCH_CAP_PSDP_NO
> ---
>  target/i386/cpu.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 127 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index f84fd20bb1..7faf6dfaee 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3866,6 +3866,133 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>              { /* end of list */ }
>          }
>      },
> +    {
> +        .name = "EmeraldRapids",
> +        .level = 0x20,
> +        .vendor = CPUID_VENDOR_INTEL,
> +        .family = 6,
> +        .model = 207,
> +        .stepping = 1,
> +        .features[FEAT_1_EDX] =
> +            CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
> +            CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
> +            CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
> +            CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
> +            CPUID_SSE | CPUID_SSE2,
> +        .features[FEAT_1_ECX] =
> +            CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
> +            CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
> +            CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
> +            CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
> +            CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> +        .features[FEAT_8000_0001_EDX] =
> +            CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
> +            CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
> +        .features[FEAT_8000_0001_ECX] =
> +            CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
> +        .features[FEAT_8000_0008_EBX] =
> +            CPUID_8000_0008_EBX_WBNOINVD,
> +        .features[FEAT_7_0_EBX] =
> +            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
> +            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> +            CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
> +            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
> +            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
> +            CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
> +            CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
> +            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
> +        .features[FEAT_7_0_ECX] =
> +            CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> +            CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
> +            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> +            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> +            CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
> +            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
> +        .features[FEAT_7_0_EDX] =
> +            CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
> +            CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
> +            CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
> +            CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
> +            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> +        .features[FEAT_ARCH_CAPABILITIES] =
> +            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
> +            MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
> +            MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
> +            MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
> +            MSR_ARCH_CAP_PSDP_NO,
> +        .features[FEAT_XSAVE] =
> +            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> +            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
> +        .features[FEAT_6_EAX] =
> +            CPUID_6_EAX_ARAT,
> +        .features[FEAT_7_1_EAX] =
> +            CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
> +            CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
> +        .features[FEAT_VMX_BASIC] =
> +            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
> +        .features[FEAT_VMX_ENTRY_CTLS] =
> +            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
> +            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
> +            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
> +        .features[FEAT_VMX_EPT_VPID_CAPS] =
> +            MSR_VMX_EPT_EXECONLY |
> +            MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
> +            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
> +            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
> +            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
> +            MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
> +            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
> +            MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
> +            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
> +        .features[FEAT_VMX_EXIT_CTLS] =
> +            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
> +            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> +            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> +            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> +            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> +        .features[FEAT_VMX_MISC] =
> +            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> +            MSR_VMX_MISC_VMWRITE_VMEXIT,
> +        .features[FEAT_VMX_PINBASED_CTLS] =
> +            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
> +            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
> +            VMX_PIN_BASED_POSTED_INTR,
> +        .features[FEAT_VMX_PROCBASED_CTLS] =
> +            VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
> +            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
> +            VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
> +            VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
> +            VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
> +            VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
> +            VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
> +            VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
> +            VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
> +            VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
> +            VMX_CPU_BASED_PAUSE_EXITING |
> +            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
> +        .features[FEAT_VMX_SECONDARY_CTLS] =
> +            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> +            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
> +            VMX_SECONDARY_EXEC_RDTSCP |
> +            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
> +            VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
> +            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
> +            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
> +            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
> +            VMX_SECONDARY_EXEC_RDRAND_EXITING |
> +            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
> +            VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
> +            VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
> +            VMX_SECONDARY_EXEC_XSAVES,
> +        .features[FEAT_VMX_VMFUNC] =
> +            MSR_VMX_VMFUNC_EPT_SWITCHING,
> +        .xlevel = 0x80000008,
> +        .model_id = "Intel Xeon Processor (EmeraldRapids)",
> +        .versions = (X86CPUVersionDefinition[]) {
> +            { .version = 1 },
> +            { /* end of list */ },
> +        },
> +    },
>      {
>          .name = "Denverton",
>          .level = 21,

Re: [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids

[Xiaoyao Li]

On 6/26/2023 8:56 PM, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:10 +0800
> Tao Su<tao1.su@linux.intel.com>  wrote:
> 
>> From: Qian Wen<qian.wen@intel.com>
>>
>> Emerald Rapids (EMR) is the next generation of Xeon server processor
>> after Sapphire Rapids (SPR).
>>
>> Currently, regarding the feature set that can be exposed to guest, there
>> isn't any one new comparing with SPR cpu model, except that EMR has a
>> different model number.
>>
>> Though it's practicable to define EMR as an alias of a new version of
>> SPR by only updating the model number and model name, it loses the
>> flexibility when new version of EMR cpu model are needed for adding new
>> features (that hasn't virtalized/supported by KVM yet).
> Which begs a question, why do we need EMR model (or alias) at all
> if it's the same as SPR at the moment.
> 
> Make new features supported 1st and only then introduce a new CPU model.
> 

Even if no new feature (that can be virtualized and exposed to guest) in 
EMR compared to SPR in the end, I think it still makes sense to provide 
a dedicated EMR CPU model in QEMU. Because
1) User will know EMR, Intel's next generation of Xeon after SRP, is 
supported by QEMU, via -cpu ?/ -cpu help;
2) It's convenient for user to create an EMR VM. People may not care 
that much what the difference between "-cpu SapphireRapids" with "-cpu 
EmeraldRapids", while they do want to create an VM which shows the CPU 
is EmeraldRapids.

Re: [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids

[Igor Mammedov]

On Tue, 27 Jun 2023 13:54:23 +0800
Xiaoyao Li <xiaoyao.li@intel.com> wrote:

> On 6/26/2023 8:56 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:10 +0800
> > Tao Su<tao1.su@linux.intel.com>  wrote:
> >   
> >> From: Qian Wen<qian.wen@intel.com>
> >>
> >> Emerald Rapids (EMR) is the next generation of Xeon server processor
> >> after Sapphire Rapids (SPR).
> >>
> >> Currently, regarding the feature set that can be exposed to guest, there
> >> isn't any one new comparing with SPR cpu model, except that EMR has a
> >> different model number.
> >>
> >> Though it's practicable to define EMR as an alias of a new version of
> >> SPR by only updating the model number and model name, it loses the
> >> flexibility when new version of EMR cpu model are needed for adding new
> >> features (that hasn't virtalized/supported by KVM yet).  
> > Which begs a question, why do we need EMR model (or alias) at all
> > if it's the same as SPR at the moment.
> > 
> > Make new features supported 1st and only then introduce a new CPU model.
> >   
> 
> Even if no new feature (that can be virtualized and exposed to guest) in 
> EMR compared to SPR in the end, I think it still makes sense to provide 
> a dedicated EMR CPU model in QEMU. Because
> 1) User will know EMR, Intel's next generation of Xeon after SRP, is 
> supported by QEMU, via -cpu ?/ -cpu help;

I don't see any benefits in misleading user by showing EMR model which is
nothing else but SPR one.
On negative side you would increase maintenance burden by introducing
extra versions of CPU model later. Which by itself is abusing versioning,
mainly used for fixing CPU bugs, by using it for adding new features.

> 2) It's convenient for user to create an EMR VM. People may not care 
> that much what the difference between "-cpu SapphireRapids" with "-cpu 
> EmeraldRapids", while they do want to create an VM which shows the CPU 
> is EmeraldRapids.
>
My guess would be is that you need guest to show EMR for developing EMR
features/guest bringup, in that case do it in your fork, and once
support is actually ready publish completed patches for it.

To exaggerate you reasoning further, we should create CPU models for
all future planned Intel/AMD CPU as a one of currently existing in
QEMU right now and then sometime in future implement features that
actually make those models what they should be.

It's downright confusing for user, so I'd object to this approach.

Re: [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids

[Xiaoyao Li]

On 6/27/2023 4:49 PM, Igor Mammedov wrote:
> On Tue, 27 Jun 2023 13:54:23 +0800
> Xiaoyao Li <xiaoyao.li@intel.com> wrote:
> 
>> On 6/26/2023 8:56 PM, Igor Mammedov wrote:
>>> On Fri, 16 Jun 2023 11:23:10 +0800
>>> Tao Su<tao1.su@linux.intel.com>  wrote:
>>>    
>>>> From: Qian Wen<qian.wen@intel.com>
>>>>
>>>> Emerald Rapids (EMR) is the next generation of Xeon server processor
>>>> after Sapphire Rapids (SPR).
>>>>
>>>> Currently, regarding the feature set that can be exposed to guest, there
>>>> isn't any one new comparing with SPR cpu model, except that EMR has a
>>>> different model number.
>>>>
>>>> Though it's practicable to define EMR as an alias of a new version of
>>>> SPR by only updating the model number and model name, it loses the
>>>> flexibility when new version of EMR cpu model are needed for adding new
>>>> features (that hasn't virtalized/supported by KVM yet).
>>> Which begs a question, why do we need EMR model (or alias) at all
>>> if it's the same as SPR at the moment.
>>>
>>> Make new features supported 1st and only then introduce a new CPU model.
>>>    
>>
>> Even if no new feature (that can be virtualized and exposed to guest) in
>> EMR compared to SPR in the end, I think it still makes sense to provide
>> a dedicated EMR CPU model in QEMU. Because
>> 1) User will know EMR, Intel's next generation of Xeon after SRP, is
>> supported by QEMU, via -cpu ?/ -cpu help;
> 
> I don't see any benefits in misleading user by showing EMR model which is
> nothing else but SPR one.
> On negative side you would increase maintenance burden by introducing
> extra versions of CPU model later. Which by itself is abusing versioning,
> mainly used for fixing CPU bugs, by using it for adding new features.
> 
>> 2) It's convenient for user to create an EMR VM. People may not care
>> that much what the difference between "-cpu SapphireRapids" with "-cpu
>> EmeraldRapids", while they do want to create an VM which shows the CPU
>> is EmeraldRapids.
>>
> My guess would be is that you need guest to show EMR for developing EMR
> features/guest bringup, in that case do it in your fork, and once
> support is actually ready publish completed patches for it.

No. I meant for CSPs who want to provide an EMR virtual machine to their 
customers, or lab admin provides an EMR (virtual) machine to its user.

Without a dedicated EmeraldRapids cpu model provided by QEMU, they need 
to use something like

   -cpu SapphireRapids,model=207,model-id="Intel Xeon Processor 
(EmeraldRapids)"

It's likely that no difference in supported features between SPR cpu 
model and EMR cpu model in the end. If so, will QEMU choose to provide a 
dedicated CPU model for EMR? or just document somewhere to QEMU users 
that "if you want to create an virtual machine with EMR cpu model, 
please go with SPR cpu model while changing it's model number to EMR's 
207 and changing model-id to tell EmeraldRapids" ?

> To exaggerate you reasoning further, we should create CPU models for
> all future planned Intel/AMD CPU as a one of currently existing in
> QEMU right now and then sometime in future implement features that
> actually make those models what they should be.

No, it's not the purpose. In fact, we're not adding an temporary EMR cpu 
model while planing to complement it in the future. Instead, we are 
adding an official EMR cpu model. The fact is, in terms of the features 
that are virtualizable and can be exposed to guest, there is no 
difference between SPR and EMR.

This comes to a basic question：Will QEMU provide a EMR cpu model even if 
no difference to SPR cpu model except the model number?

> It's downright confusing for user, so I'd object to this approach.
> 

Re: [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids

[Daniel P. Berrangé]

On Tue, Jun 27, 2023 at 07:25:21PM +0800, Xiaoyao Li wrote:
> On 6/27/2023 4:49 PM, Igor Mammedov wrote:
> > On Tue, 27 Jun 2023 13:54:23 +0800
> > Xiaoyao Li <xiaoyao.li@intel.com> wrote:
> > 
> > > On 6/26/2023 8:56 PM, Igor Mammedov wrote:
> > > > On Fri, 16 Jun 2023 11:23:10 +0800
> > > > Tao Su<tao1.su@linux.intel.com>  wrote:
> > > > > From: Qian Wen<qian.wen@intel.com>
> > > > > 
> > > > > Emerald Rapids (EMR) is the next generation of Xeon server processor
> > > > > after Sapphire Rapids (SPR).
> > > > > 
> > > > > Currently, regarding the feature set that can be exposed to guest, there
> > > > > isn't any one new comparing with SPR cpu model, except that EMR has a
> > > > > different model number.
> > > > > 
> > > > > Though it's practicable to define EMR as an alias of a new version of
> > > > > SPR by only updating the model number and model name, it loses the
> > > > > flexibility when new version of EMR cpu model are needed for adding new
> > > > > features (that hasn't virtalized/supported by KVM yet).
> > > > Which begs a question, why do we need EMR model (or alias) at all
> > > > if it's the same as SPR at the moment.
> > > > 
> > > > Make new features supported 1st and only then introduce a new CPU model.
> > > 
> > > Even if no new feature (that can be virtualized and exposed to guest) in
> > > EMR compared to SPR in the end, I think it still makes sense to provide
> > > a dedicated EMR CPU model in QEMU. Because
> > > 1) User will know EMR, Intel's next generation of Xeon after SRP, is
> > > supported by QEMU, via -cpu ?/ -cpu help;
> > 
> > I don't see any benefits in misleading user by showing EMR model which is
> > nothing else but SPR one.
> > On negative side you would increase maintenance burden by introducing
> > extra versions of CPU model later. Which by itself is abusing versioning,
> > mainly used for fixing CPU bugs, by using it for adding new features.
> > 
> > > 2) It's convenient for user to create an EMR VM. People may not care
> > > that much what the difference between "-cpu SapphireRapids" with "-cpu
> > > EmeraldRapids", while they do want to create an VM which shows the CPU
> > > is EmeraldRapids.
> > > 
> > My guess would be is that you need guest to show EMR for developing EMR
> > features/guest bringup, in that case do it in your fork, and once
> > support is actually ready publish completed patches for it.
> 
> No. I meant for CSPs who want to provide an EMR virtual machine to their
> customers, or lab admin provides an EMR (virtual) machine to its user.
> 
> Without a dedicated EmeraldRapids cpu model provided by QEMU, they need to
> use something like
> 
>   -cpu SapphireRapids,model=207,model-id="Intel Xeon Processor
> (EmeraldRapids)"
>
> It's likely that no difference in supported features between SPR cpu model
> and EMR cpu model in the end. If so, will QEMU choose to provide a dedicated
> CPU model for EMR? or just document somewhere to QEMU users that "if you
> want to create an virtual machine with EMR cpu model, please go with SPR cpu
> model while changing it's model number to EMR's 207 and changing model-id to
> tell EmeraldRapids" ?

I think QEMU's answer would be to not bother trying todo this at all,
just expose '-cpu SapphireRapids', because there's no functional benefit
to overriding the model ID, when all the CPUID features are identical.

Those who have the guest to see the *perfect* functional match of the
host still have '-cpu host' available.

The named CPU models are for the case where we want a rough approximation
for a CPU generation available, to easy migration across mixed CPU clusters.
Given the intent is to have a rough approximation, there's no compelling
reason to add an exact EmeraldRapids named CPU.

> > To exaggerate you reasoning further, we should create CPU models for
> > all future planned Intel/AMD CPU as a one of currently existing in
> > QEMU right now and then sometime in future implement features that
> > actually make those models what they should be.
> 
> No, it's not the purpose. In fact, we're not adding an temporary EMR cpu
> model while planing to complement it in the future. Instead, we are adding
> an official EMR cpu model. The fact is, in terms of the features that are
> virtualizable and can be exposed to guest, there is no difference between
> SPR and EMR.
> 
> This comes to a basic question：Will QEMU provide a EMR cpu model even if no
> difference to SPR cpu model except the model number?

Historically we have generally only added new CPU models if there was
a feature difference. We've skipped adding many of the Intel models
that didn't add bring new features, on the basis that there is no
compelling functional need to have them.

With regards,
Daniel
-- 
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[PATCH 7/7] target/i386: Add new CPU model GraniteRapids

[Tao Su]

The GraniteRapids CPU model mainly adds the following new features based
on SapphireRapids:

- PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
- MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
- SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
- FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
 target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 136 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7faf6dfaee..860106fc24 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3993,6 +3993,142 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             { /* end of list */ },
         },
     },
+    {
+        .name = "GraniteRapids",
+        .level = 0x20,
+        .vendor = CPUID_VENDOR_INTEL,
+        .family = 6,
+        .model = 173,
+        .stepping = 0,
+        /*
+         * please keep the ascending order so that we can have a clear view of
+         * bit position of each feature.
+         */
+        .features[FEAT_1_EDX] =
+            CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+            CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+            CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+            CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
+            CPUID_SSE | CPUID_SSE2,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
+            CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
+            CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+            CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
+            CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
+        .features[FEAT_8000_0008_EBX] =
+            CPUID_8000_0008_EBX_WBNOINVD,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
+            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
+            CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
+            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
+            CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
+            CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
+            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
+            CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
+            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
+            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
+            CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
+            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
+            CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
+            CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
+            CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
+            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
+            MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
+            MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
+            MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
+            MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .features[FEAT_7_1_EAX] =
+            CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
+            CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
+            CPUID_7_1_EAX_AMX_FP16,
+        .features[FEAT_7_1_EDX] =
+            CPUID_7_1_EDX_PREFETCHITI,
+        .features[FEAT_7_2_EDX] =
+            CPUID_7_2_EDX_MCDT_NO,
+        .features[FEAT_VMX_BASIC] =
+            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+        .features[FEAT_VMX_ENTRY_CTLS] =
+            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+        .features[FEAT_VMX_EPT_VPID_CAPS] =
+            MSR_VMX_EPT_EXECONLY |
+            MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
+            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
+            MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+        .features[FEAT_VMX_EXIT_CTLS] =
+            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
+            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+        .features[FEAT_VMX_MISC] =
+            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+            MSR_VMX_MISC_VMWRITE_VMEXIT,
+        .features[FEAT_VMX_PINBASED_CTLS] =
+            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+            VMX_PIN_BASED_POSTED_INTR,
+        .features[FEAT_VMX_PROCBASED_CTLS] =
+            VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
+            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
+            VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
+            VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
+            VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
+            VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
+            VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
+            VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
+            VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
+            VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
+            VMX_CPU_BASED_PAUSE_EXITING |
+            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+        .features[FEAT_VMX_SECONDARY_CTLS] =
+            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+            VMX_SECONDARY_EXEC_RDTSCP |
+            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+            VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
+            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+            VMX_SECONDARY_EXEC_RDRAND_EXITING |
+            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+            VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+            VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
+            VMX_SECONDARY_EXEC_XSAVES,
+        .features[FEAT_VMX_VMFUNC] =
+            MSR_VMX_VMFUNC_EPT_SWITCHING,
+        .xlevel = 0x80000008,
+        .model_id = "Intel Xeon Processor (GraniteRapids)",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            { /* end of list */ },
+        },
+    },
     {
         .name = "Denverton",
         .level = 21,
-- 
2.34.1

Re: [PATCH 7/7] target/i386: Add new CPU model GraniteRapids

[Igor Mammedov]

On Fri, 16 Jun 2023 11:23:11 +0800
Tao Su <tao1.su@linux.intel.com> wrote:

> The GraniteRapids CPU model mainly adds the following new features based
> on SapphireRapids:
> 
> - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
> - SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
> - FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
> - PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
> - PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]

Can you point me to a some doc where above features
are are documented as being introduced by GraniteRapids?

 
> Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> Tested-by: Xuelian Guo <xuelian.guo@intel.com>
> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
>  target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 136 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 7faf6dfaee..860106fc24 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3993,6 +3993,142 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>              { /* end of list */ },
>          },
>      },
> +    {
> +        .name = "GraniteRapids",
> +        .level = 0x20,
> +        .vendor = CPUID_VENDOR_INTEL,
> +        .family = 6,
> +        .model = 173,
> +        .stepping = 0,
> +        /*
> +         * please keep the ascending order so that we can have a clear view of
> +         * bit position of each feature.
> +         */
> +        .features[FEAT_1_EDX] =
> +            CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
> +            CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
> +            CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
> +            CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
> +            CPUID_SSE | CPUID_SSE2,
> +        .features[FEAT_1_ECX] =
> +            CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
> +            CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
> +            CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
> +            CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
> +            CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> +        .features[FEAT_8000_0001_EDX] =
> +            CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
> +            CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
> +        .features[FEAT_8000_0001_ECX] =
> +            CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
> +        .features[FEAT_8000_0008_EBX] =
> +            CPUID_8000_0008_EBX_WBNOINVD,
> +        .features[FEAT_7_0_EBX] =
> +            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
> +            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> +            CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
> +            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
> +            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
> +            CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
> +            CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
> +            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
> +        .features[FEAT_7_0_ECX] =
> +            CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> +            CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
> +            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> +            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> +            CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
> +            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
> +        .features[FEAT_7_0_EDX] =
> +            CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
> +            CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
> +            CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
> +            CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
> +            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> +        .features[FEAT_ARCH_CAPABILITIES] =
> +            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
> +            MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
> +            MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
> +            MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
> +            MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
> +        .features[FEAT_XSAVE] =
> +            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> +            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
> +        .features[FEAT_6_EAX] =
> +            CPUID_6_EAX_ARAT,
> +        .features[FEAT_7_1_EAX] =
> +            CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
> +            CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
> +            CPUID_7_1_EAX_AMX_FP16,
> +        .features[FEAT_7_1_EDX] =
> +            CPUID_7_1_EDX_PREFETCHITI,
> +        .features[FEAT_7_2_EDX] =
> +            CPUID_7_2_EDX_MCDT_NO,
> +        .features[FEAT_VMX_BASIC] =
> +            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
> +        .features[FEAT_VMX_ENTRY_CTLS] =
> +            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
> +            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
> +            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
> +        .features[FEAT_VMX_EPT_VPID_CAPS] =
> +            MSR_VMX_EPT_EXECONLY |
> +            MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
> +            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
> +            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
> +            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
> +            MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
> +            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
> +            MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
> +            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
> +        .features[FEAT_VMX_EXIT_CTLS] =
> +            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
> +            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> +            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> +            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> +            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> +        .features[FEAT_VMX_MISC] =
> +            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> +            MSR_VMX_MISC_VMWRITE_VMEXIT,
> +        .features[FEAT_VMX_PINBASED_CTLS] =
> +            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
> +            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
> +            VMX_PIN_BASED_POSTED_INTR,
> +        .features[FEAT_VMX_PROCBASED_CTLS] =
> +            VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
> +            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
> +            VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
> +            VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
> +            VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
> +            VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
> +            VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
> +            VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
> +            VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
> +            VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
> +            VMX_CPU_BASED_PAUSE_EXITING |
> +            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
> +        .features[FEAT_VMX_SECONDARY_CTLS] =
> +            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> +            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
> +            VMX_SECONDARY_EXEC_RDTSCP |
> +            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
> +            VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
> +            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
> +            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
> +            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
> +            VMX_SECONDARY_EXEC_RDRAND_EXITING |
> +            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
> +            VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
> +            VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
> +            VMX_SECONDARY_EXEC_XSAVES,
> +        .features[FEAT_VMX_VMFUNC] =
> +            MSR_VMX_VMFUNC_EPT_SWITCHING,
> +        .xlevel = 0x80000008,
> +        .model_id = "Intel Xeon Processor (GraniteRapids)",
> +        .versions = (X86CPUVersionDefinition[]) {
> +            { .version = 1 },
> +            { /* end of list */ },
> +        },
> +    },
>      {
>          .name = "Denverton",
>          .level = 21,

Re: [PATCH 7/7] target/i386: Add new CPU model GraniteRapids

[Tao Su]

On Tue, Jun 27, 2023 at 01:55:23PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:11 +0800
> Tao Su <tao1.su@linux.intel.com> wrote:
> 
> > The GraniteRapids CPU model mainly adds the following new features based
> > on SapphireRapids:
> > 
> > - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
> > - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
> > - MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
> > - SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
> > - FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
> > - PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
> > - PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
> 
> Can you point me to a some doc where above features
> are are documented as being introduced by GraniteRapids?

Sure. For PREFETCHITI and AMX-FP16, Intel ISE[1] lists them as GraniteRapids new
features, but the last five mainly indicate the HW contains the security fix for
corresponding vulnerabilities, which not list there. I dump the CPUIDs/MSRs
from the physical machine and get these added features.

[1] https://cdrdv2.intel.com/v1/dl/getContent/671368

Thanks,
Tao

> 
>  
> > Signed-off-by: Tao Su <tao1.su@linux.intel.com>
> > Tested-by: Xuelian Guo <xuelian.guo@intel.com>
> > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
> > ---
> >  target/i386/cpu.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 136 insertions(+)
> > 
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 7faf6dfaee..860106fc24 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -3993,6 +3993,142 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> >              { /* end of list */ },
> >          },
> >      },
> > +    {
> > +        .name = "GraniteRapids",
> > +        .level = 0x20,
> > +        .vendor = CPUID_VENDOR_INTEL,
> > +        .family = 6,
> > +        .model = 173,
> > +        .stepping = 0,
> > +        /*
> > +         * please keep the ascending order so that we can have a clear view of
> > +         * bit position of each feature.
> > +         */
> > +        .features[FEAT_1_EDX] =
> > +            CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
> > +            CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
> > +            CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
> > +            CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
> > +            CPUID_SSE | CPUID_SSE2,
> > +        .features[FEAT_1_ECX] =
> > +            CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
> > +            CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
> > +            CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
> > +            CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
> > +            CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> > +        .features[FEAT_8000_0001_EDX] =
> > +            CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
> > +            CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
> > +        .features[FEAT_8000_0001_ECX] =
> > +            CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
> > +        .features[FEAT_8000_0008_EBX] =
> > +            CPUID_8000_0008_EBX_WBNOINVD,
> > +        .features[FEAT_7_0_EBX] =
> > +            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
> > +            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> > +            CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
> > +            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
> > +            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
> > +            CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
> > +            CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
> > +            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
> > +        .features[FEAT_7_0_ECX] =
> > +            CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> > +            CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
> > +            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> > +            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> > +            CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
> > +            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
> > +        .features[FEAT_7_0_EDX] =
> > +            CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
> > +            CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
> > +            CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
> > +            CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
> > +            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> > +        .features[FEAT_ARCH_CAPABILITIES] =
> > +            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
> > +            MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
> > +            MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
> > +            MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
> > +            MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
> > +        .features[FEAT_XSAVE] =
> > +            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> > +            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
> > +        .features[FEAT_6_EAX] =
> > +            CPUID_6_EAX_ARAT,
> > +        .features[FEAT_7_1_EAX] =
> > +            CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
> > +            CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
> > +            CPUID_7_1_EAX_AMX_FP16,
> > +        .features[FEAT_7_1_EDX] =
> > +            CPUID_7_1_EDX_PREFETCHITI,
> > +        .features[FEAT_7_2_EDX] =
> > +            CPUID_7_2_EDX_MCDT_NO,
> > +        .features[FEAT_VMX_BASIC] =
> > +            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
> > +        .features[FEAT_VMX_ENTRY_CTLS] =
> > +            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
> > +            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
> > +            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
> > +        .features[FEAT_VMX_EPT_VPID_CAPS] =
> > +            MSR_VMX_EPT_EXECONLY |
> > +            MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
> > +            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
> > +            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
> > +            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
> > +            MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
> > +            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
> > +            MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
> > +            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
> > +        .features[FEAT_VMX_EXIT_CTLS] =
> > +            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
> > +            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> > +            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> > +            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> > +            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> > +        .features[FEAT_VMX_MISC] =
> > +            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> > +            MSR_VMX_MISC_VMWRITE_VMEXIT,
> > +        .features[FEAT_VMX_PINBASED_CTLS] =
> > +            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
> > +            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
> > +            VMX_PIN_BASED_POSTED_INTR,
> > +        .features[FEAT_VMX_PROCBASED_CTLS] =
> > +            VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
> > +            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
> > +            VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
> > +            VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
> > +            VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
> > +            VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
> > +            VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
> > +            VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
> > +            VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
> > +            VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
> > +            VMX_CPU_BASED_PAUSE_EXITING |
> > +            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
> > +        .features[FEAT_VMX_SECONDARY_CTLS] =
> > +            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
> > +            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
> > +            VMX_SECONDARY_EXEC_RDTSCP |
> > +            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
> > +            VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
> > +            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
> > +            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
> > +            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
> > +            VMX_SECONDARY_EXEC_RDRAND_EXITING |
> > +            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
> > +            VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
> > +            VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
> > +            VMX_SECONDARY_EXEC_XSAVES,
> > +        .features[FEAT_VMX_VMFUNC] =
> > +            MSR_VMX_VMFUNC_EPT_SWITCHING,
> > +        .xlevel = 0x80000008,
> > +        .model_id = "Intel Xeon Processor (GraniteRapids)",
> > +        .versions = (X86CPUVersionDefinition[]) {
> > +            { .version = 1 },
> > +            { /* end of list */ },
> > +        },
> > +    },
> >      {
> >          .name = "Denverton",
> >          .level = 21,
> 

Re: [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids

[Wang, Lei]

On 6/16/2023 11:23, Tao Su wrote:
> This patch series mainly updates SapphireRapids CPU model and adds
> new CPU model EmeraldRapids and GraniteRapids.
> 
> Bit 13 (ARCH_CAP_FBSDP_NO), bit 14 (ARCH_CAP_FBSDP_NO) and bit 15

Bit 13 should be MSR_ARCH_CAP_SBDR_SSDP_NO, right?

> (ARCH_CAP_PSDP_NO) of MSR_IA32_ARCH_CAPABILITIES are enumerated starting
> from latest SapphireRapids, which are missed in current SapphireRapids
> CPU model, so add a new version for SapphireRapids CPU model to expose
> these bits.
> 
> Add EmeraldRapids CPU model to this series, since EmeraldRapids also
> enumerates these bits. The original patch of EmeraldRapids CPU model is
> in [1].
> 
> GraniteRapids is Intel's successor to EmeraldRapids, an Intel 3 process
> microarchitecture for enthusiasts and servers, which adds new features
> based on SapphireRapids and EmeraldRapids.
> 
> [1]
> https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian.wen@intel.com/
> 
> Lei Wang (1):
>   target/i386: Add few security fix bits in ARCH_CAPABILITIES into
>     SapphireRapids CPU model
> 
> Qian Wen (1):
>   target/i386: Add new CPU model EmeraldRapids
> 
> Tao Su (5):
>   target/i386: Add FEAT_7_1_EDX to adjust feature level
>   target/i386: Add support for MCDT_NO in CPUID enumeration
>   target/i386: Allow MCDT_NO if host supports
>   target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
>   target/i386: Add new CPU model GraniteRapids
> 
>  target/i386/cpu.c     | 303 +++++++++++++++++++++++++++++++++++++++++-
>  target/i386/cpu.h     |   8 ++
>  target/i386/kvm/kvm.c |   5 +
>  3 files changed, 314 insertions(+), 2 deletions(-)
> 
> 
> base-commit: 7efd65423ab22e6f5890ca08ae40c84d6660242f

Re: [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids

[Tao Su]

On Fri, Jun 16, 2023 at 12:01:52PM +0800, Wang, Lei wrote:
> On 6/16/2023 11:23, Tao Su wrote:
> > This patch series mainly updates SapphireRapids CPU model and adds
> > new CPU model EmeraldRapids and GraniteRapids.
> > 
> > Bit 13 (ARCH_CAP_FBSDP_NO), bit 14 (ARCH_CAP_FBSDP_NO) and bit 15
> 
> Bit 13 should be MSR_ARCH_CAP_SBDR_SSDP_NO, right?

Yes, copied by mistake, thanks!

Tao

> 
> > (ARCH_CAP_PSDP_NO) of MSR_IA32_ARCH_CAPABILITIES are enumerated starting
> > from latest SapphireRapids, which are missed in current SapphireRapids
> > CPU model, so add a new version for SapphireRapids CPU model to expose
> > these bits.
> > 
> > Add EmeraldRapids CPU model to this series, since EmeraldRapids also
> > enumerates these bits. The original patch of EmeraldRapids CPU model is
> > in [1].
> > 
> > GraniteRapids is Intel's successor to EmeraldRapids, an Intel 3 process
> > microarchitecture for enthusiasts and servers, which adds new features
> > based on SapphireRapids and EmeraldRapids.
> > 
> > [1]
> > https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian.wen@intel.com/
> > 
> > Lei Wang (1):
> >   target/i386: Add few security fix bits in ARCH_CAPABILITIES into
> >     SapphireRapids CPU model
> > 
> > Qian Wen (1):
> >   target/i386: Add new CPU model EmeraldRapids
> > 
> > Tao Su (5):
> >   target/i386: Add FEAT_7_1_EDX to adjust feature level
> >   target/i386: Add support for MCDT_NO in CPUID enumeration
> >   target/i386: Allow MCDT_NO if host supports
> >   target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
> >   target/i386: Add new CPU model GraniteRapids
> > 
> >  target/i386/cpu.c     | 303 +++++++++++++++++++++++++++++++++++++++++-
> >  target/i386/cpu.h     |   8 ++
> >  target/i386/kvm/kvm.c |   5 +
> >  3 files changed, 314 insertions(+), 2 deletions(-)
> > 
> > 
> > base-commit: 7efd65423ab22e6f5890ca08ae40c84d6660242f