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[99.254.144.39]) by smtp.gmail.com with ESMTPSA id e24-20020ac84918000000b003f9af049c55sm903218qtq.18.2023.07.06.12.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 12:02:20 -0700 (PDT) Date: Thu, 6 Jul 2023 15:02:07 -0400 From: Peter Xu To: "Michael S. Tsirkin" Cc: Leonardo Bras Soares Passos , Marcel Apfelbaum , Juan Quintela , qemu-devel@nongnu.org Subject: Re: [PATCH v2 1/1] pcie: Add hotplug detect state register to cmask Message-ID: References: <20230706045546.593605-3-leobras@redhat.com> <20230706144844-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20230706144844-mutt-send-email-mst@kernel.org> Received-SPF: pass client-ip=170.10.129.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jul 06, 2023 at 02:50:20PM -0400, Michael S. Tsirkin wrote: > On Thu, Jul 06, 2023 at 02:14:37PM -0400, Peter Xu wrote: > > On Thu, Jul 06, 2023 at 03:07:40PM -0300, Leonardo Bras Soares Passos wrote: > > > > I asked the same question, and I still keep confused: whether there's a > > > > first bad commit? Starting from when it fails? > > > > > > > > For example, is this broken on 6.0 binaries too with pc-q35-6.0? > > > > > > I tested for qemu 6.0, and it still reproduces, but have not pursued > > > this any further. > > > > I see, thanks! > > > > But then do you know why it's never hit before? I assume it means this bug > > has been there for a long time. > > It's a race - you have to migrate after the bit has been set before > the bit got cleared. > cmask is exactly for bits that qemu modifies itself. Michael, do you mean that Leo's patch is wrong? I just got understood why it got cleared - I think Leo didn't mention that the device was actually offlined before migration, IIUC that's why the PDS bit got cleared, if PDS was trying to describe that of the slot. According to: /* Used to enable checks on load. Note that writable bits are * never checked even if set in cmask. */ uint8_t *cmask; It does sound reasonable to me to have PDS cleared when device offlined. Since hypervisor doesn't really know what the condition the slot presence bit would be when migrating, it seems we should just clear the bit in cmask. So with the last reply from Leo, the patch looks all right to me. It's just that as Leo mentioned, we should mention the offline process if that's the case, because that's definitely an important step to reproduce the issue. Thanks, -- Peter Xu