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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id b18-20020adfe312000000b0031437ec7ec1sm8433034wrj.2.2023.07.29.14.31.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jul 2023 14:31:10 -0700 (PDT) Date: Sat, 29 Jul 2023 22:31:09 +0100 From: Stafford Horne To: QEMU Development Subject: Re: [PATCH] target/openrisc: Set EPCR to next PC on FPE exceptions Message-ID: References: <20230729210851.3097340-1-shorne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230729210851.3097340-1-shorne@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=shorne@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Jul 29, 2023 at 10:08:51PM +0100, Stafford Horne wrote: > The architecture specification calls for the EPCR to be set to "Address > of next not executed instruction" when there is a floating point > exception (FPE). This was not being done, so fix it by using the same > method as syscall. Note, this may need a lot more work if we start > seeing floating point operations in delay slots which exceptions > enabled. It should be "with exceptions enabled." > > Without this patch FPU exceptions will loop, as the exception hanlding "handling" > will always return back to the failed floating point instruction. > > This was not noticed in earlier testing because: > > 1. The compiler usually generates code which clobbers the input operand > such as: > > lf.div.s r19,r17,r19 > > 2. The target will store the operation output before to the register > before handling the exception. So an operation such as: > > float a = 100.0f; > float b = 0.0f; > float c = a / b; /* lf.div.s r19,r17,r19 */ > > Will first execute: > > 100 / 0 -> Store inf to c (r19) > -> triggering divide by zero exception > -> handle and return > > Then it will exectute: > > 100 / inf -> Store 0 to c (no exception) > > To confirm the looping behavoid and the fix I used the following: "behavior" > float fpu_div(float a, float b) { > float c; > asm volatile("lf.div.s %0, %1, %2" > : "+r" (c) > : "r" (a), "r" (b)); > return c; > } > > Signed-off-by: Stafford Horne -Stafford > --- > target/openrisc/interrupt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c > index 3887812810..9b14b8a2c6 100644 > --- a/target/openrisc/interrupt.c > +++ b/target/openrisc/interrupt.c > @@ -34,7 +34,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) > int exception = cs->exception_index; > > env->epcr = env->pc; > - if (exception == EXCP_SYSCALL) { > + if (exception == EXCP_SYSCALL || exception == EXCP_FPE) { > env->epcr += 4; > } > /* When we have an illegal instruction the error effective address > -- > 2.39.1 >