* [PATCH 0/1] Added support for the MMU node in the RHCT @ 2023-07-31 22:09 Lilly Anderson 2023-07-31 22:09 ` [PATCH 1/1] " Lilly Anderson 0 siblings, 1 reply; 4+ messages in thread From: Lilly Anderson @ 2023-07-31 22:09 UTC (permalink / raw) To: qemu-devel, qemu-riscv; +Cc: Lilly Anderson The specification was recently updated so I thought I'd submit a patch. This does not add support for the CMO node, as I am unsure whether its pre-requisites are implemented. Lilly Anderson (1): Added support for the MMU node in the RHCT hw/riscv/virt-acpi-build.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) -- 2.41.0 Signed-off-by: Lilly Anderson <fermium@anarchist.gay> ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/1] Added support for the MMU node in the RHCT 2023-07-31 22:09 [PATCH 0/1] Added support for the MMU node in the RHCT Lilly Anderson @ 2023-07-31 22:09 ` Lilly Anderson 2023-08-02 13:37 ` Alistair Francis 0 siblings, 1 reply; 4+ messages in thread From: Lilly Anderson @ 2023-07-31 22:09 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Lilly Anderson, Sunil V L, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei --- hw/riscv/virt-acpi-build.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 7331248f59..cb36e52169 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -119,7 +119,8 @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) /* * ACPI spec, Revision 6.5+ * 5.2.36 RISC-V Hart Capabilities Table (RHCT) - * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/18 + * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view */ static void build_rhct(GArray *table_data, @@ -133,6 +134,7 @@ static void build_rhct(GArray *table_data, uint32_t isa_offset, num_rhct_nodes; RISCVCPU *cpu; char *isa; + uint8_t mmu_type; AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, .oem_table_id = s->oem_table_id }; @@ -145,8 +147,8 @@ static void build_rhct(GArray *table_data, build_append_int_noprefix(table_data, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8); - /* ISA + N hart info */ - num_rhct_nodes = 1 + ms->smp.cpus; + /* ISA + MMU + N hart info */ + num_rhct_nodes = 2 + ms->smp.cpus; /* Number of RHCT nodes*/ build_append_int_noprefix(table_data, num_rhct_nodes, 4); @@ -174,6 +176,15 @@ static void build_rhct(GArray *table_data, build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ } + /* MMU Node */ + build_append_int_noprefix(table_data, 2, 2); /* Type 2 */ + build_append_int_noprefix(table_data, 8, 2); /* Length */ + build_append_int_noprefix(table_data, 1, 2); /* Revision */ + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ + + mmu_type = satp_mode_max_from_map(riscv_cpu_cfg(&cpu->env)->satp_mode.map) - 8; + build_append_int_noprefix(table_data, mmu_type, 1); /* MMU Type */ + /* Hart Info Node */ for (int i = 0; i < arch_ids->len; i++) { build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ -- 2.41.0 Signed-off-by: Lilly Anderson <fermium@anarchist.gay> ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] Added support for the MMU node in the RHCT 2023-07-31 22:09 ` [PATCH 1/1] " Lilly Anderson @ 2023-08-02 13:37 ` Alistair Francis 2023-08-02 13:46 ` Sunil V L 0 siblings, 1 reply; 4+ messages in thread From: Alistair Francis @ 2023-08-02 13:37 UTC (permalink / raw) To: Lilly Anderson Cc: qemu-devel, qemu-riscv, Sunil V L, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei On Mon, Jul 31, 2023 at 6:22 PM Lilly Anderson <fermium@anarchist.gay> wrote: > Hello, Thanks for the patch. Do you mind writing a commit message here. You will also need to include a signed-off-by line, see https://www.qemu.org/docs/master/devel/submitting-a-patch.html#patch-emails-must-include-a-signed-off-by-line > --- > hw/riscv/virt-acpi-build.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index 7331248f59..cb36e52169 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -119,7 +119,8 @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) > /* > * ACPI spec, Revision 6.5+ > * 5.2.36 RISC-V Hart Capabilities Table (RHCT) > - * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 > + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/18 > + * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view > * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view > */ > static void build_rhct(GArray *table_data, > @@ -133,6 +134,7 @@ static void build_rhct(GArray *table_data, > uint32_t isa_offset, num_rhct_nodes; > RISCVCPU *cpu; > char *isa; > + uint8_t mmu_type; > > AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, > .oem_table_id = s->oem_table_id }; > @@ -145,8 +147,8 @@ static void build_rhct(GArray *table_data, > build_append_int_noprefix(table_data, > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8); > > - /* ISA + N hart info */ > - num_rhct_nodes = 1 + ms->smp.cpus; > + /* ISA + MMU + N hart info */ > + num_rhct_nodes = 2 + ms->smp.cpus; I think it's worth adding a comment that we aren't including CMO, as the spec says: "and at least one CMO node for systems with harts implementing CMO extensions." Alistair > > /* Number of RHCT nodes*/ > build_append_int_noprefix(table_data, num_rhct_nodes, 4); > @@ -174,6 +176,15 @@ static void build_rhct(GArray *table_data, > build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ > } > > + /* MMU Node */ > + build_append_int_noprefix(table_data, 2, 2); /* Type 2 */ > + build_append_int_noprefix(table_data, 8, 2); /* Length */ > + build_append_int_noprefix(table_data, 1, 2); /* Revision */ > + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ > + > + mmu_type = satp_mode_max_from_map(riscv_cpu_cfg(&cpu->env)->satp_mode.map) - 8; > + build_append_int_noprefix(table_data, mmu_type, 1); /* MMU Type */ > + > /* Hart Info Node */ > for (int i = 0; i < arch_ids->len; i++) { > build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ > -- > 2.41.0 > > Signed-off-by: Lilly Anderson <fermium@anarchist.gay> > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/1] Added support for the MMU node in the RHCT 2023-08-02 13:37 ` Alistair Francis @ 2023-08-02 13:46 ` Sunil V L 0 siblings, 0 replies; 4+ messages in thread From: Sunil V L @ 2023-08-02 13:46 UTC (permalink / raw) To: Alistair Francis Cc: Lilly Anderson, qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei Hi Lilly, I have already sent patch series [1] which includes MMU node patch [2]. I am preparing v2 of that series based on the feedback I received. [1] - https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02657.html [2] - https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02667.html Thanks, Sunil On Wed, Aug 02, 2023 at 09:37:40AM -0400, Alistair Francis wrote: > On Mon, Jul 31, 2023 at 6:22 PM Lilly Anderson <fermium@anarchist.gay> wrote: > > > > Hello, > > Thanks for the patch. > > Do you mind writing a commit message here. You will also need to > include a signed-off-by line, see > https://www.qemu.org/docs/master/devel/submitting-a-patch.html#patch-emails-must-include-a-signed-off-by-line > > > --- > > hw/riscv/virt-acpi-build.c | 17 ++++++++++++++--- > > 1 file changed, 14 insertions(+), 3 deletions(-) > > > > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > > index 7331248f59..cb36e52169 100644 > > --- a/hw/riscv/virt-acpi-build.c > > +++ b/hw/riscv/virt-acpi-build.c > > @@ -119,7 +119,8 @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) > > /* > > * ACPI spec, Revision 6.5+ > > * 5.2.36 RISC-V Hart Capabilities Table (RHCT) > > - * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 > > + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/18 > > + * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view > > * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view > > */ > > static void build_rhct(GArray *table_data, > > @@ -133,6 +134,7 @@ static void build_rhct(GArray *table_data, > > uint32_t isa_offset, num_rhct_nodes; > > RISCVCPU *cpu; > > char *isa; > > + uint8_t mmu_type; > > > > AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, > > .oem_table_id = s->oem_table_id }; > > @@ -145,8 +147,8 @@ static void build_rhct(GArray *table_data, > > build_append_int_noprefix(table_data, > > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8); > > > > - /* ISA + N hart info */ > > - num_rhct_nodes = 1 + ms->smp.cpus; > > + /* ISA + MMU + N hart info */ > > + num_rhct_nodes = 2 + ms->smp.cpus; > > I think it's worth adding a comment that we aren't including CMO, as > the spec says: > > "and at least one CMO node for systems with harts implementing CMO extensions." > > Alistair > > > > > /* Number of RHCT nodes*/ > > build_append_int_noprefix(table_data, num_rhct_nodes, 4); > > @@ -174,6 +176,15 @@ static void build_rhct(GArray *table_data, > > build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ > > } > > > > + /* MMU Node */ > > + build_append_int_noprefix(table_data, 2, 2); /* Type 2 */ > > + build_append_int_noprefix(table_data, 8, 2); /* Length */ > > + build_append_int_noprefix(table_data, 1, 2); /* Revision */ > > + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ > > + > > + mmu_type = satp_mode_max_from_map(riscv_cpu_cfg(&cpu->env)->satp_mode.map) - 8; > > + build_append_int_noprefix(table_data, mmu_type, 1); /* MMU Type */ > > + > > /* Hart Info Node */ > > for (int i = 0; i < arch_ids->len; i++) { > > build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ > > -- > > 2.41.0 > > > > Signed-off-by: Lilly Anderson <fermium@anarchist.gay> > > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-08-02 13:47 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-07-31 22:09 [PATCH 0/1] Added support for the MMU node in the RHCT Lilly Anderson 2023-07-31 22:09 ` [PATCH 1/1] " Lilly Anderson 2023-08-02 13:37 ` Alistair Francis 2023-08-02 13:46 ` Sunil V L
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