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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id z1-20020a05600c220100b003fc01f7b415sm5902582wml.39.2023.08.10.12.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Aug 2023 12:50:29 -0700 (PDT) Date: Thu, 10 Aug 2023 20:50:29 +0100 From: Stafford Horne To: Michael Tokarev Cc: QEMU Development , Richard Henderson Subject: Re: [PULL 1/1] target/openrisc: Set EPCR to next PC on FPE exceptions Message-ID: References: <20230809203432.424071-1-shorne@gmail.com> <20230809203432.424071-2-shorne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=shorne@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Aug 10, 2023 at 09:35:18AM +0300, Michael Tokarev wrote: > 09.08.2023 23:34, Stafford Horne пишет: > > The architecture specification calls for the EPCR to be set to "Address > > of next not executed instruction" when there is a floating point > > exception (FPE). This was not being done, so fix it by using the same > > pattern as syscall. Also, we move this logic down to be done for > > instructions not in the delay slot as called for by the architecture > > manual. > > > > Without this patch FPU exceptions will loop, as the exception handling > > will always return back to the failed floating point instruction. > > > > This was not noticed in earlier testing because: > > > > 1. The compiler usually generates code which clobbers the input operand > > such as: > > > > lf.div.s r19,r17,r19 > > > > 2. The target will store the operation output before to the register > > before handling the exception. So an operation such as: > > > > float a = 100.0f; > > float b = 0.0f; > > float c = a / b; /* lf.div.s r19,r17,r19 */ > > > > Will first execute: > > > > 100 / 0 -> Store inf to c (r19) > > -> triggering divide by zero exception > > -> handle and return > > > > Then it will execute: > > > > 100 / inf -> Store 0 to c (no exception) > > > > To confirm the looping behavior and the fix I used the following: > > > > float fpu_div(float a, float b) { > > float c; > > asm volatile("lf.div.s %0, %1, %2" > > : "+r" (c) > > : "r" (a), "r" (b)); > > return c; > > } > > Is it a -stable material? It applies cleanly to 8.0 and 7.2. > Or maybe it is not needed on older versions, not being noticed before? I would say no, it will work on 8.0 an 7.2 but this code path is not very useful withouth the other 8.1 Floating Point Exception handling updates. -Stafford