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[34.135.64.30]) by smtp.gmail.com with ESMTPSA id v12-20020a92d24c000000b00345d6e8ded4sm1252896ilg.25.2023.09.01.12.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Sep 2023 12:23:23 -0700 (PDT) Date: Fri, 1 Sep 2023 19:23:20 +0000 From: Colton Lewis To: Andrew Jones Cc: qemu-devel@nongnu.org, Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, qemu-trivial@nongnu.org Subject: Re: [PATCH] arm64: Restore trapless ptimer access Message-ID: References: <20230831190052.129045-1-coltonlewis@google.com> <20230901-16232ff17690fc32a0feb5df@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230901-16232ff17690fc32a0feb5df@orel> Received-SPF: pass client-ip=2607:f8b0:4864:20::134; envelope-from=coltonlewis@google.com; helo=mail-il1-x134.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Sep 01, 2023 at 09:35:47AM +0200, Andrew Jones wrote: > On Thu, Aug 31, 2023 at 07:00:52PM +0000, Colton Lewis wrote: > > Due to recent KVM changes, QEMU is setting a ptimer offset resulting > > in unintended trap and emulate access and a consequent performance > > hit. Filter out the PTIMER_CNT register to restore trapless ptimer > > access. > > > > Quoting Andrew Jones: > > > > Simply reading the CNT register and writing back the same value is > > enough to set an offset, since the timer will have certainly moved > > past whatever value was read by the time it's written. QEMU > > frequently saves and restores all registers in the get-reg-list array, > > unless they've been explicitly filtered out (with Linux commit > > 680232a94c12, KVM_REG_ARM_PTIMER_CNT is now in the array). So, to > > restore trapless ptimer accesses, we need a QEMU patch to filter out > > the register. > > > > See > > https://lore.kernel.org/kvmarm/gsntttsonus5.fsf@coltonlewis-kvm.c.googlers.com/T/#m0770023762a821db2a3f0dd0a7dc6aa54e0d0da9 > > The link can be shorter with > > https://lore.kernel.org/all/20230823200408.1214332-1-coltonlewis@google.com/ I will keep that in mind next time. > > for additional context. > > > > Signed-off-by: Andrew Jones > > Thanks for the testing and posting, Colton. Please add your s-o-b and a > Tested-by tag as well. Assuming it is sufficient to add here instead of reposting the whole patch: Signed-off-by: Colton Lewis Tested-by: Colton Lewis > > --- > > target/arm/kvm64.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c > > index 4d904a1d11..2dd46e0a99 100644 > > --- a/target/arm/kvm64.c > > +++ b/target/arm/kvm64.c > > @@ -672,6 +672,7 @@ typedef struct CPRegStateLevel { > > */ > > static const CPRegStateLevel non_runtime_cpregs[] = { > > { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE }, > > + { KVM_REG_ARM_PTIMER_CNT, KVM_PUT_FULL_STATE }, > > }; > > > > int kvm_arm_cpreg_level(uint64_t regidx) > > -- > > 2.42.0.283.g2d96d420d3-goog > >